From bd5f9f45d120dc78f12e2c2c3caea305bde948e4 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 3 Dec 2014 05:22:32 +0000 Subject: [PATCH] R600/SI: Fix suspicious indexing The loop is over the operands of an instruction, and checks the register with the sub reg index of the dest register. This probably meant to be checking the sub reg index of the same operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223205 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIFixSGPRCopies.cpp | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/lib/Target/R600/SIFixSGPRCopies.cpp b/lib/Target/R600/SIFixSGPRCopies.cpp index c7a16f4c387..d90f09d3cd6 100644 --- a/lib/Target/R600/SIFixSGPRCopies.cpp +++ b/lib/Target/R600/SIFixSGPRCopies.cpp @@ -219,11 +219,13 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { case AMDGPU::PHI: { DEBUG(dbgs() << "Fixing PHI: " << MI); - for (unsigned i = 1; i < MI.getNumOperands(); i+=2) { - unsigned Reg = MI.getOperand(i).getReg(); - const TargetRegisterClass *RC = inferRegClassFromDef(TRI, MRI, Reg, - MI.getOperand(0).getSubReg()); - MRI.constrainRegClass(Reg, RC); + for (unsigned i = 1; i < MI.getNumOperands(); i += 2) { + const MachineOperand &Op = MI.getOperand(i); + unsigned Reg = Op.getReg(); + const TargetRegisterClass *RC + = inferRegClassFromDef(TRI, MRI, Reg, Op.getSubReg()); + + MRI.constrainRegClass(Op.getReg(), RC); } unsigned Reg = MI.getOperand(0).getReg(); const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg,