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https://github.com/c64scene-ar/llvm-6502.git
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Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103903 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
ded05e34b6
commit
bd91ea53f8
@ -656,12 +656,12 @@ PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
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let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
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def ADJCALLSTACKUP :
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PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
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"@ ADJCALLSTACKUP $amt1",
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"${:comment} ADJCALLSTACKUP $amt1",
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[(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
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def ADJCALLSTACKDOWN :
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PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
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"@ ADJCALLSTACKDOWN $amt",
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"${:comment} ADJCALLSTACKDOWN $amt",
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[(ARMcallseq_start timm:$amt)]>;
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}
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@ -795,7 +795,7 @@ def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
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// binutils
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let isBarrier = 1, isTerminator = 1 in
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def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
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".long 0xe7ffdefe @ trap", [(trap)]>,
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".long 0xe7ffdefe ${:comment} trap", [(trap)]>,
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Requires<[IsARM]> {
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let Inst{27-25} = 0b011;
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let Inst{24-20} = 0b11111;
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@ -2533,12 +2533,12 @@ let Defs =
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def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
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AddrModeNone, SizeSpecial, IndexModeNone,
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Pseudo, NoItinerary,
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"str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
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"str\tsp, [$src, #+8] ${:comment} eh_setjmp begin\n\t"
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"add\t$val, pc, #8\n\t"
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"str\t$val, [$src, #+4]\n\t"
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"mov\tr0, #0\n\t"
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"add\tpc, pc, #0\n\t"
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"mov\tr0, #1 @ eh_setjmp end", "",
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"mov\tr0, #1 ${:comment} eh_setjmp end", "",
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[(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
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Requires<[IsARM, HasVFP2]>;
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}
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@ -2548,12 +2548,12 @@ let Defs =
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def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
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AddrModeNone, SizeSpecial, IndexModeNone,
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Pseudo, NoItinerary,
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"str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
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"str\tsp, [$src, #+8] ${:comment} eh_setjmp begin\n\t"
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"add\t$val, pc, #8\n\t"
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"str\t$val, [$src, #+4]\n\t"
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"mov\tr0, #0\n\t"
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"add\tpc, pc, #0\n\t"
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"mov\tr0, #1 @ eh_setjmp end", "",
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"mov\tr0, #1 ${:comment} eh_setjmp end", "",
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[(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
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Requires<[IsARM, NoVFP]>;
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}
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@ -2819,10 +2819,10 @@ def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
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// Pseudo vector move instructions for QQ and QQQQ registers. This should
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// be expanded after register allocation is completed.
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def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
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NoItinerary, "@ vmov\t$dst, $src", []>;
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NoItinerary, "${:comment} vmov\t$dst, $src", []>;
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def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
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NoItinerary, "@ vmov\t$dst, $src", []>;
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NoItinerary, "${:comment} vmov\t$dst, $src", []>;
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} // neverHasSideEffects
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// VMOV : Vector Move (Immediate)
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@ -127,12 +127,12 @@ def t_addrmode_sp : Operand<i32>,
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let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
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def tADJCALLSTACKUP :
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PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
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"@ tADJCALLSTACKUP $amt1",
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"${:comment} tADJCALLSTACKUP $amt1",
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[(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
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def tADJCALLSTACKDOWN :
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PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
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"@ tADJCALLSTACKDOWN $amt",
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"${:comment} tADJCALLSTACKDOWN $amt",
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[(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
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}
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@ -254,14 +254,14 @@ def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
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// Pseudo instruction that will expand into a tSUBspi + a copy.
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let usesCustomInserter = 1 in { // Expanded after instruction selection.
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def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs),
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NoItinerary, "@ sub\t$dst, $rhs", []>;
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NoItinerary, "${:comment} sub\t$dst, $rhs", []>;
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def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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NoItinerary, "@ add\t$dst, $rhs", []>;
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NoItinerary, "${:comment} add\t$dst, $rhs", []>;
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let Defs = [CPSR] in
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def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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NoItinerary, "@ and\t$dst, $rhs", []>;
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NoItinerary, "${:comment} and\t$dst, $rhs", []>;
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} // usesCustomInserter
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//===----------------------------------------------------------------------===//
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@ -374,7 +374,7 @@ let isBranch = 1, isTerminator = 1 in {
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// Far jump
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let Defs = [LR] in
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def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
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"bl\t$target\t@ far jump",[]>;
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"bl\t$target\t${:comment} far jump",[]>;
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def tBR_JTr : T1JTI<(outs),
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(ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
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@ -423,7 +423,7 @@ def tSVC : T1pI<(outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", []>,
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// binutils
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let isBarrier = 1, isTerminator = 1 in
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def tTRAP : TI<(outs), (ins), IIC_Br,
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".word 0xdefe @ trap", [(trap)]>, Encoding16 {
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".word 0xdefe ${:comment} trap", [(trap)]>, Encoding16 {
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let Inst{15-12} = 0b1101;
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let Inst{11-8} = 0b1110;
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}
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@ -870,7 +870,7 @@ def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
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let usesCustomInserter = 1 in // Expanded after instruction selection.
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def tMOVCCr_pseudo :
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PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
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NoItinerary, "@ tMOVCCr $cc",
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NoItinerary, "${:comment} tMOVCCr $cc",
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[/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
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@ -922,13 +922,13 @@ let Defs =
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[ R0, R1, R2, R3, R4, R5, R6, R7, R12 ] in {
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def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
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AddrModeNone, SizeSpecial, NoItinerary,
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"str\t$val, [$src, #8]\t@ begin eh.setjmp\n"
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"str\t$val, [$src, #8]\t${:comment} begin eh.setjmp\n"
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"\tmov\t$val, pc\n"
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"\tadds\t$val, #9\n"
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"\tstr\t$val, [$src, #4]\n"
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"\tmovs\tr0, #0\n"
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"\tb\t1f\n"
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"\tmovs\tr0, #1\t@ end eh.setjmp\n"
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"\tmovs\tr0, #1\t${:comment} end eh.setjmp\n"
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"1:", "",
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[(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
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}
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@ -1015,7 +1015,7 @@ def : T1Pat<(i32 imm0_255_comp:$src),
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// scheduling.
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let isReMaterializable = 1 in
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def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
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NoItinerary, "@ ldr.n\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
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NoItinerary, "${:comment} ldr.n\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
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[(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
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imm:$cp))]>,
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Requires<[IsThumb1Only]>;
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@ -888,11 +888,11 @@ def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
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// Pseudo instruction that will expand into a t2SUBrSPi + a copy.
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let usesCustomInserter = 1 in { // Expanded after instruction selection.
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def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
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NoItinerary, "@ sub.w\t$dst, $sp, $imm", []>;
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NoItinerary, "${:comment} sub.w\t$dst, $sp, $imm", []>;
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def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
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NoItinerary, "@ subw\t$dst, $sp, $imm", []>;
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NoItinerary, "${:comment} subw\t$dst, $sp, $imm", []>;
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def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
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NoItinerary, "@ sub\t$dst, $sp, $rhs", []>;
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NoItinerary, "${:comment} sub\t$dst, $sp, $rhs", []>;
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} // usesCustomInserter
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@ -2394,13 +2394,13 @@ let Defs =
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D31 ] in {
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def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
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AddrModeNone, SizeSpecial, NoItinerary,
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"str\t$val, [$src, #8]\t@ begin eh.setjmp\n"
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"str\t$val, [$src, #8]\t${:comment} begin eh.setjmp\n"
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"\tmov\t$val, pc\n"
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"\tadds\t$val, #9\n"
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"\tstr\t$val, [$src, #4]\n"
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"\tmovs\tr0, #0\n"
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"\tb\t1f\n"
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"\tmovs\tr0, #1\t@ end eh.setjmp\n"
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"\tmovs\tr0, #1\t${:comment} end eh.setjmp\n"
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"1:", "",
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[(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
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Requires<[IsThumb2, HasVFP2]>;
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@ -2410,13 +2410,13 @@ let Defs =
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[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ] in {
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def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
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AddrModeNone, SizeSpecial, NoItinerary,
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"str\t$val, [$src, #8]\t@ begin eh.setjmp\n"
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"str\t$val, [$src, #8]\t${:comment} begin eh.setjmp\n"
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"\tmov\t$val, pc\n"
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"\tadds\t$val, #9\n"
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"\tstr\t$val, [$src, #4]\n"
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"\tmovs\tr0, #0\n"
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"\tb\t1f\n"
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"\tmovs\tr0, #1\t@ end eh.setjmp\n"
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"\tmovs\tr0, #1\t${:comment} end eh.setjmp\n"
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"1:", "",
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[(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
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Requires<[IsThumb2, NoVFP]>;
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@ -2688,7 +2688,7 @@ def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
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// scheduling.
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
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NoItinerary, "@ ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
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NoItinerary, "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
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[(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
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imm:$cp))]>,
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Requires<[IsThumb2]>;
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