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Revert a part of r126557 which could create unschedulable DAGs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134067 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1310,16 +1310,6 @@ SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
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return SDValue();
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}
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/// isCarryMaterialization - Returns true if V is an ADDE node that is known to
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/// return 0 or 1 depending on the carry flag.
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static bool isCarryMaterialization(SDValue V) {
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if (V.getOpcode() != ISD::ADDE)
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return false;
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(0));
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return C && C->isNullValue() && V.getOperand(0) == V.getOperand(1);
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}
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SDValue DAGCombiner::visitADD(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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@ -1483,18 +1473,6 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
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return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
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}
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// add (adde 0, 0, glue), X -> adde X, 0, glue
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if (N0->hasOneUse() && isCarryMaterialization(N0))
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return DAG.getNode(ISD::ADDE, N->getDebugLoc(),
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DAG.getVTList(VT, MVT::Glue), N1, N0.getOperand(0),
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N0.getOperand(2));
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// add X, (adde 0, 0, glue) -> adde X, 0, glue
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if (N1->hasOneUse() && isCarryMaterialization(N1))
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return DAG.getNode(ISD::ADDE, N->getDebugLoc(),
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DAG.getVTList(VT, MVT::Glue), N0, N1.getOperand(0),
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N1.getOperand(2));
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return SDValue();
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}
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@ -1538,16 +1516,6 @@ SDValue DAGCombiner::visitADDC(SDNode *N) {
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N->getDebugLoc(), MVT::Glue));
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}
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// addc (adde 0, 0, glue), X -> adde X, 0, glue
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if (N0->hasOneUse() && isCarryMaterialization(N0))
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return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N1,
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DAG.getConstant(0, VT), N0.getOperand(2));
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// addc X, (adde 0, 0, glue) -> adde X, 0, glue
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if (N1->hasOneUse() && isCarryMaterialization(N1))
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return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N0,
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DAG.getConstant(0, VT), N1.getOperand(2));
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return SDValue();
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}
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@ -1,5 +1,4 @@
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; RUN: llc -march=x86-64 < %s | FileCheck %s -check-prefix=CHECK-64
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; RUN: llc -march=x86 < %s | FileCheck %s -check-prefix=CHECK-32
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define void @a(i64* nocapture %s, i64* nocapture %t, i64 %a, i64 %b, i64 %c) nounwind {
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entry:
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@ -16,11 +15,6 @@ entry:
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store i64 %8, i64* %t, align 8
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ret void
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; CHECK-32: addl
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; CHECK-32: adcl
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; CHECK-32: adcl $0
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; CHECK-32: adcl $0
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; CHECK-64: addq
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; CHECK-64: adcq $0
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}
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