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[AArch64] Robustize atomic cmpxchg test a little more. NFC.
We changed the test to test non-constant values in r238049. We can also use CHECK-NEXT to be a little stricter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238052 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha
parent
7e80a67d35
commit
bde8616229
@ -1,51 +1,51 @@
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; RUN: llc < %s -march=arm64 -verify-machineinstrs -mcpu=cyclone | FileCheck %s
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; RUN: llc < %s -march=arm64 -asm-verbose=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
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define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) {
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define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) #0 {
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; CHECK-LABEL: val_compare_and_swap:
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; CHECK: ubfx x[[NEWVAL_REG:[0-9]+]], x2, #0, #32
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxr [[RESULT:w[0-9]+]], [x0]
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; CHECK: cmp [[RESULT]], w1
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; CHECK: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
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; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], w[[NEWVAL_REG]], [x0]
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; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
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; CHECK: [[LABEL2]]:
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; CHECK-NEXT: ubfx x[[NEWVAL_REG:[0-9]+]], x2, #0, #32
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; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x0]
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; CHECK-NEXT: cmp [[RESULT]], w1
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; CHECK-NEXT: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], w[[NEWVAL_REG]], [x0]
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; CHECK-NEXT: cbnz [[SCRATCH_REG]], [[LABEL]]
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; CHECK-NEXT: [[LABEL2]]:
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%pair = cmpxchg i32* %p, i32 %cmp, i32 %new acquire acquire
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%val = extractvalue { i32, i1 } %pair, 0
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ret i32 %val
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}
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define i32 @val_compare_and_swap_rel(i32* %p, i32 %cmp, i32 %new) {
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define i32 @val_compare_and_swap_rel(i32* %p, i32 %cmp, i32 %new) #0 {
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; CHECK-LABEL: val_compare_and_swap_rel:
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; CHECK: ubfx x[[NEWVAL_REG:[0-9]+]], x2, #0, #32
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxr [[RESULT:w[0-9]+]], [x0]
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; CHECK: cmp [[RESULT]], w1
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; CHECK: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
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; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], w[[NEWVAL_REG]], [x0]
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; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
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; CHECK: [[LABEL2]]:
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; CHECK-NEXT: ubfx x[[NEWVAL_REG:[0-9]+]], x2, #0, #32
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; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x0]
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; CHECK-NEXT: cmp [[RESULT]], w1
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; CHECK-NEXT: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: stlxr [[SCRATCH_REG:w[0-9]+]], w[[NEWVAL_REG]], [x0]
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; CHECK-NEXT: cbnz [[SCRATCH_REG]], [[LABEL]]
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; CHECK-NEXT: [[LABEL2]]:
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%pair = cmpxchg i32* %p, i32 %cmp, i32 %new acq_rel monotonic
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%val = extractvalue { i32, i1 } %pair, 0
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ret i32 %val
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}
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define i64 @val_compare_and_swap_64(i64* %p, i64 %cmp, i64 %new) {
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define i64 @val_compare_and_swap_64(i64* %p, i64 %cmp, i64 %new) #0 {
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; CHECK-LABEL: val_compare_and_swap_64:
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; CHECK: mov x[[ADDR:[0-9]+]], x0
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldxr [[RESULT:x[0-9]+]], [x[[ADDR]]]
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; CHECK: cmp [[RESULT]], x1
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; CHECK: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
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; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]]
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; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
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; CHECK: [[LABEL2]]:
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; CHECK-NEXT: mov x[[ADDR:[0-9]+]], x0
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; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK-NEXT: ldxr [[RESULT:x[0-9]+]], [x[[ADDR]]]
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; CHECK-NEXT: cmp [[RESULT]], x1
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; CHECK-NEXT: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]]
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; CHECK-NEXT: cbnz [[SCRATCH_REG]], [[LABEL]]
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; CHECK-NEXT: [[LABEL2]]:
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%pair = cmpxchg i64* %p, i64 %cmp, i64 %new monotonic monotonic
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%val = extractvalue { i64, i1 } %pair, 0
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ret i64 %val
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}
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define i32 @fetch_and_nand(i32* %p) {
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define i32 @fetch_and_nand(i32* %p) #0 {
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; CHECK-LABEL: fetch_and_nand:
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldxr w[[DEST_REG:[0-9]+]], [x0]
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@ -59,7 +59,7 @@ define i32 @fetch_and_nand(i32* %p) {
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ret i32 %val
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}
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define i64 @fetch_and_nand_64(i64* %p) {
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define i64 @fetch_and_nand_64(i64* %p) #0 {
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; CHECK-LABEL: fetch_and_nand_64:
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; CHECK: mov x[[ADDR:[0-9]+]], x0
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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@ -73,7 +73,7 @@ define i64 @fetch_and_nand_64(i64* %p) {
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ret i64 %val
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}
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define i32 @fetch_and_or(i32* %p) {
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define i32 @fetch_and_or(i32* %p) #0 {
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; CHECK-LABEL: fetch_and_or:
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; CHECK: movz [[OLDVAL_REG:w[0-9]+]], #0x5
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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@ -87,7 +87,7 @@ define i32 @fetch_and_or(i32* %p) {
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ret i32 %val
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}
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define i64 @fetch_and_or_64(i64* %p) {
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define i64 @fetch_and_or_64(i64* %p) #0 {
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; CHECK: fetch_and_or_64:
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; CHECK: mov x[[ADDR:[0-9]+]], x0
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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@ -99,35 +99,35 @@ define i64 @fetch_and_or_64(i64* %p) {
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ret i64 %val
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}
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define void @acquire_fence() {
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define void @acquire_fence() #0 {
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fence acquire
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ret void
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; CHECK-LABEL: acquire_fence:
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; CHECK: dmb ishld
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}
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define void @release_fence() {
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define void @release_fence() #0 {
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fence release
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ret void
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; CHECK-LABEL: release_fence:
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; CHECK: dmb ish{{$}}
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}
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define void @seq_cst_fence() {
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define void @seq_cst_fence() #0 {
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fence seq_cst
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ret void
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; CHECK-LABEL: seq_cst_fence:
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; CHECK: dmb ish{{$}}
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}
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define i32 @atomic_load(i32* %p) {
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define i32 @atomic_load(i32* %p) #0 {
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%r = load atomic i32, i32* %p seq_cst, align 4
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ret i32 %r
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; CHECK-LABEL: atomic_load:
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; CHECK: ldar
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}
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define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) {
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define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) #0 {
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; CHECK-LABEL: atomic_load_relaxed_8:
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%ptr_unsigned = getelementptr i8, i8* %p, i32 4095
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%val_unsigned = load atomic i8, i8* %ptr_unsigned monotonic, align 1
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@ -152,7 +152,7 @@ define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) {
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ret i8 %tot3
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}
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define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) {
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define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) #0 {
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; CHECK-LABEL: atomic_load_relaxed_16:
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%ptr_unsigned = getelementptr i16, i16* %p, i32 4095
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%val_unsigned = load atomic i16, i16* %ptr_unsigned monotonic, align 2
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@ -177,7 +177,7 @@ define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) {
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ret i16 %tot3
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}
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define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) {
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define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) #0 {
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; CHECK-LABEL: atomic_load_relaxed_32:
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%ptr_unsigned = getelementptr i32, i32* %p, i32 4095
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%val_unsigned = load atomic i32, i32* %ptr_unsigned monotonic, align 4
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@ -202,7 +202,7 @@ define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) {
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ret i32 %tot3
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}
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define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) {
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define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) #0 {
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; CHECK-LABEL: atomic_load_relaxed_64:
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%ptr_unsigned = getelementptr i64, i64* %p, i32 4095
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%val_unsigned = load atomic i64, i64* %ptr_unsigned monotonic, align 8
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@ -228,14 +228,14 @@ define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) {
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}
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define void @atomc_store(i32* %p) {
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define void @atomc_store(i32* %p) #0 {
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store atomic i32 4, i32* %p seq_cst, align 4
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ret void
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; CHECK-LABEL: atomc_store:
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; CHECK: stlr
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}
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define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) {
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define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) #0 {
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; CHECK-LABEL: atomic_store_relaxed_8:
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%ptr_unsigned = getelementptr i8, i8* %p, i32 4095
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store atomic i8 %val, i8* %ptr_unsigned monotonic, align 1
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@ -257,7 +257,7 @@ define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) {
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ret void
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}
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define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) {
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define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) #0 {
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; CHECK-LABEL: atomic_store_relaxed_16:
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%ptr_unsigned = getelementptr i16, i16* %p, i32 4095
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store atomic i16 %val, i16* %ptr_unsigned monotonic, align 2
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@ -279,7 +279,7 @@ define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) {
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ret void
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}
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define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) {
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define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) #0 {
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; CHECK-LABEL: atomic_store_relaxed_32:
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%ptr_unsigned = getelementptr i32, i32* %p, i32 4095
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store atomic i32 %val, i32* %ptr_unsigned monotonic, align 4
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@ -301,7 +301,7 @@ define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) {
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ret void
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}
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define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) {
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define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) #0 {
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; CHECK-LABEL: atomic_store_relaxed_64:
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%ptr_unsigned = getelementptr i64, i64* %p, i32 4095
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store atomic i64 %val, i64* %ptr_unsigned monotonic, align 8
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@ -347,3 +347,5 @@ return: ; preds = %if.else, %entry
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%retval.0 = phi i32 [ %add.i2, %if.else ], [ %add.i, %entry ]
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ret i32 %retval.0
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}
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attributes #0 = { nounwind }
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