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Add FastISel support for several more binary operators.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55020 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2008-08-20 00:11:48 +00:00
parent 108ecf3975
commit bdedd44773
3 changed files with 101 additions and 18 deletions
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include/llvm/CodeGen/FastISel.h
+31
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@@ -50,22 +50,53 @@ protected:
virtual ~FastISel();
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type and opcode
/// be emitted.
virtual unsigned FastEmit_(MVT::SimpleValueType VT,
ISD::NodeType Opcode);
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operand be emitted.
///
virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
ISD::NodeType Opcode, unsigned Op0);
/// FastEmit_rr - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operands be emitted.
///
virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
ISD::NodeType Opcode,
unsigned Op0, unsigned Op1);
/// FastEmitInst_ - Emit a MachineInstr with no operands and a
/// result register in the given register class.
///
unsigned FastEmitInst_(unsigned MachineInstOpcode,
const TargetRegisterClass *RC);
/// FastEmitInst_ - Emit a MachineInstr with one register operand
/// and a result register in the given register class.
///
unsigned FastEmitInst_r(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0);
/// FastEmitInst_ - Emit a MachineInstr with two register operands
/// and a result register in the given register class.
///
unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, unsigned Op1);
private:
bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
DenseMap<const Value*, unsigned> &ValueMap);
bool SelectGetElementPtr(Instruction *I,
DenseMap<const Value*, unsigned> &ValueMap);
};
}