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Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106917 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -912,6 +912,14 @@ let Constraints = "$src1 = $dst" in {
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/// SSE 1 Only
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// Aliases for intrinsics
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let isAsmParserOnly = 1, Pattern = []<dag> in {
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defm Int_VCVTTSS2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
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int_x86_sse_cvttss2si, f32mem, load,
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"cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS;
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defm Int_VCVTTSD2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
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int_x86_sse2_cvttsd2si, f128mem, load,
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"cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD;
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}
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defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
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f32mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
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XS;
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@ -919,6 +927,13 @@ defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
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f128mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
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XD;
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let isAsmParserOnly = 1, Pattern = []<dag> in {
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defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
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"cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
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defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load,
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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SSEPackedSingle>, TB, VEX;
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}
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let Pattern = []<dag> in {
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defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
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"cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
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@ -10806,3 +10806,19 @@
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// CHECK: encoding: [0xc5,0xe8,0x12,0xd9]
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vmovhlps %xmm1, %xmm2, %xmm3
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// CHECK: vcvtss2sil %xmm1, %eax
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// CHECK: encoding: [0xc5,0xfa,0x2d,0xc1]
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vcvtss2si %xmm1, %eax
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// CHECK: vcvtss2sil (%eax), %ebx
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// CHECK: encoding: [0xc5,0xfa,0x2d,0x18]
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vcvtss2si (%eax), %ebx
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// CHECK: vcvtdq2ps %xmm5, %xmm6
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// CHECK: encoding: [0xc5,0xf8,0x5b,0xf5]
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vcvtdq2ps %xmm5, %xmm6
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// CHECK: vcvtdq2ps (%eax), %xmm6
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// CHECK: encoding: [0xc5,0xf8,0x5b,0x30]
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vcvtdq2ps (%eax), %xmm6
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@ -854,4 +854,19 @@ pshufb CPI1_0(%rip), %xmm1
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// CHECK: encoding: [0xc4,0x41,0x18,0x12,0xeb]
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vmovhlps %xmm11, %xmm12, %xmm13
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// CHECK: vcvtss2sil %xmm11, %eax
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// CHECK: encoding: [0xc4,0xc1,0x7a,0x2d,0xc3]
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vcvtss2si %xmm11, %eax
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// CHECK: vcvtss2sil (%rax), %ebx
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// CHECK: encoding: [0xc5,0xfa,0x2d,0x18]
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vcvtss2si (%rax), %ebx
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// CHECK: vcvtdq2ps %xmm10, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x78,0x5b,0xe2]
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vcvtdq2ps %xmm10, %xmm12
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// CHECK: vcvtdq2ps (%rax), %xmm12
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// CHECK: encoding: [0xc5,0x78,0x5b,0x20]
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vcvtdq2ps (%rax), %xmm12
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