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R600: Fix 64-bit integer division

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This fixes a failure in one of the oclconform tests.

Patch by: Jan Vesely

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222073 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-11-15 01:07:57 +00:00
parent 57b2b0c4da
commit be11bdfe20
1 changed files with 2 additions and 2 deletions
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4
lib/Target/R600/AMDGPUISelLowering.cpp
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@ -1618,7 +1618,7 @@ void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETGE);
SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
@ -1626,7 +1626,7 @@ void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETGE);
REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
}