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really kill off the last MRMInitReg inst, remove logic from encoder.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95437 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-02-05 21:34:18 +00:00
parent 28c1d29b09
commit be1778fea7
4 changed files with 9 additions and 17 deletions
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1
lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
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@ -384,6 +384,7 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
case X86::MMX_V_SETALLONES:
LowerUnaryToTwoAddr(OutMI, X86::MMX_PCMPEQDrr); break;
case X86::FsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
case X86::V_SET0: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;

3
lib/Target/X86/X86Instr64bit.td
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@ -1610,8 +1610,7 @@ def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
// when we have a better way to specify isel priority.
let Defs = [EFLAGS],
AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins),
"",
def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
[(set GR64:$dst, 0)]>;
// Materialize i64 constant where top 32-bits are zero. This could theoretically

10
lib/Target/X86/X86InstrSSE.td
View File

@ -506,9 +506,9 @@ def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
canFoldAsLoad = 1 in
// FIXME: Set encoding to pseudo!
def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
"", [(set FR32:$dst, fp32imm0)]>,
Requires<[HasSSE1]>, TB, OpSize;
def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
[(set FR32:$dst, fp32imm0)]>,
Requires<[HasSSE1]>, TB, OpSize;
// Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
// disregarded.
@ -1270,8 +1270,8 @@ def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
// Alias instructions that map fld0 to pxor for sse.
let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
canFoldAsLoad = 1 in
def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
"pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
[(set FR64:$dst, fpimm0)]>,
Requires<[HasSSE2]>, TB, OpSize;
// Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are

12
lib/Target/X86/X86MCCodeEmitter.cpp
View File

@ -364,10 +364,10 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
--NumOps;
// FIXME: Can we kill off MRMInitReg??
unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
switch (TSFlags & X86II::FormMask) {
case X86II::MRMInitReg:
assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
case X86II::RawFrm: {
@ -547,14 +547,6 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
#endif
break;
}
case X86II::MRMInitReg:
EmitByte(BaseOpcode, OS);
// Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
EmitRegModRMByte(MI.getOperand(CurOp),
GetX86RegNum(MI.getOperand(CurOp)), OS);
++CurOp;
break;
}
#ifndef NDEBUG