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Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich 2011-03-07 21:56:36 +00:00
parent e390b3245f
commit be2119e8e2
14 changed files with 64 additions and 66 deletions
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8
include/llvm/Target/TargetLowering.h
View File

@ -190,14 +190,6 @@ public:
return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy];
}
/// getRegPressureLimit - Return the register pressure "high water mark" for
/// the specific register class. The scheduler is in high register pressure
/// mode (for the specific register class) if it goes over the limit.
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const {
return 0;
}
/// isTypeLegal - Return true if the target has native support for the
/// specified value type. This means that it has a register that directly
/// holds it without promotions or expansions.

8
include/llvm/Target/TargetRegisterInfo.h
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@ -595,6 +595,14 @@ public:
return NULL;
}
/// getRegPressureLimit - Return the register pressure "high water mark" for
/// the specific register class. The scheduler is in high register pressure
/// mode (for the specific register class) if it goes over the limit.
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const {
return 0;
}
/// getAllocationOrder - Returns the register allocation order for a specified
/// register class in the form of a pair of TargetRegisterClass iterators.
virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>

2
lib/CodeGen/MachineLICM.cpp
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@ -294,7 +294,7 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
RegLimit.resize(NumRC);
for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
E = TRI->regclass_end(); I != E; ++I)
RegLimit[(*I)->getID()] = TLI->getRegPressureLimit(*I, MF);
RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, MF);
}
// Get our Loop information...

2
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@ -1458,7 +1458,7 @@ public:
std::fill(RegPressure.begin(), RegPressure.end(), 0);
for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
E = TRI->regclass_end(); I != E; ++I)
RegLimit[(*I)->getID()] = tli->getRegPressureLimit(*I, MF);
RegLimit[(*I)->getID()] = tri->getRegPressureLimit(*I, MF);
}
}

20
lib/Target/ARM/ARMBaseRegisterInfo.cpp
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@ -348,6 +348,26 @@ ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
return ARM::GPRRegisterClass;
}
unsigned
ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
switch (RC->getID()) {
default:
return 0;
case ARM::tGPRRegClassID:
return TFI->hasFP(MF) ? 4 : 5;
case ARM::GPRRegClassID: {
unsigned FP = TFI->hasFP(MF) ? 1 : 0;
return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
}
case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
case ARM::DPRRegClassID:
return 32 - 10;
}
}
/// getAllocationOrder - Returns the register allocation order for a specified
/// register class in the form of a pair of TargetRegisterClass iterators.
std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>

3
lib/Target/ARM/ARMBaseRegisterInfo.h
View File

@ -128,6 +128,9 @@ public:
const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const;
std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
getAllocationOrder(const TargetRegisterClass *RC,
unsigned HintType, unsigned HintReg,

21
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -945,27 +945,6 @@ Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
return Sched::RegPressure;
}
// FIXME: Move to RegInfo
unsigned
ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
switch (RC->getID()) {
default:
return 0;
case ARM::tGPRRegClassID:
return TFI->hasFP(MF) ? 4 : 5;
case ARM::GPRRegClassID: {
unsigned FP = TFI->hasFP(MF) ? 1 : 0;
return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
}
case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
case ARM::DPRRegClassID:
return 32 - 10;
}
}
//===----------------------------------------------------------------------===//
// Lowering Code
//===----------------------------------------------------------------------===//

3
lib/Target/ARM/ARMISelLowering.h
View File

@ -329,9 +329,6 @@ namespace llvm {
Sched::Preference getSchedulingPreference(SDNode *N) const;
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const;
bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;

8
lib/Target/CellSPU/SPUISelLowering.h
View File

@ -183,14 +183,6 @@ namespace llvm {
virtual bool isLegalAddressingMode(const AddrMode &AM,
const Type *Ty) const;
/// After allocating this many registers, the allocator should feel
/// register pressure. The value is a somewhat random guess, based on the
/// number of non callee saved registers in the C calling convention.
virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC,
MachineFunction &MF) const{
return 50;
}
};
}

8
lib/Target/CellSPU/SPURegisterInfo.h
View File

@ -46,6 +46,14 @@ namespace llvm {
virtual const TargetRegisterClass *
getPointerRegClass(unsigned Kind = 0) const;
/// After allocating this many registers, the allocator should feel
/// register pressure. The value is a somewhat random guess, based on the
/// number of non callee saved registers in the C calling convention.
virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC,
MachineFunction &MF) const{
return 50;
}
//! Return the array of callee-saved registers
virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;

21
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1271,27 +1271,6 @@ X86TargetLowering::findRepresentativeClass(EVT VT) const{
return std::make_pair(RRC, Cost);
}
// FIXME: Why this routine is here? Move to RegInfo!
unsigned
X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
switch (RC->getID()) {
default:
return 0;
case X86::GR32RegClassID:
return 4 - FPDiff;
case X86::GR64RegClassID:
return 12 - FPDiff;
case X86::VR128RegClassID:
return Subtarget->is64Bit() ? 10 : 4;
case X86::VR64RegClassID:
return 4;
}
}
bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
unsigned &Offset) const {
if (!Subtarget->isTargetLinux())

3
lib/Target/X86/X86ISelLowering.h
View File

@ -677,9 +677,6 @@ namespace llvm {
/// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const;
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const;
/// getStackCookieLocation - Return true if the target stores stack
/// protector cookies at a fixed offset in some non-standard address
/// space, and populates the address space and offset as

20
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -340,6 +340,26 @@ X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
return NULL;
}
unsigned
X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
switch (RC->getID()) {
default:
return 0;
case X86::GR32RegClassID:
return 4 - FPDiff;
case X86::GR64RegClassID:
return 12 - FPDiff;
case X86::VR128RegClassID:
return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
case X86::VR64RegClassID:
return 4;
}
}
const unsigned *
X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
bool callsEHReturn = false;

3
lib/Target/X86/X86RegisterInfo.h
View File

@ -101,6 +101,9 @@ public:
const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass *RC) const;
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const;
/// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee-save registers on this target.
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;