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Rely on instruction format to determine so_reg operand for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56181 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -372,7 +372,11 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
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}
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}
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// Encode shifter operand.
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// Encode shifter operand.
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if (TID.getNumOperands() - OpIdx > 1)
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bool HasSoReg = (Format == ARMII::DPRdSoReg ||
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Format == ARMII::DPRnSoReg ||
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Format == ARMII::DPRSoReg ||
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Format == ARMII::DPRSoRegS);
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if (HasSoReg)
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// Encode SoReg.
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// Encode SoReg.
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return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
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return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
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