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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-20 09:24:58 +00:00
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
15246738f2
commit
be3bf42331
@ -63,7 +63,7 @@ namespace {
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int FrameIndex;
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} Base;
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bool isRIPRel; // RIP relative?
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bool isRIPRel; // RIP as base?
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unsigned Scale;
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SDOperand IndexReg;
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unsigned Disp;
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@ -664,7 +664,9 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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case X86ISD::Wrapper: {
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bool is64Bit = Subtarget->is64Bit();
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// Under X86-64 non-small code model, GV (and friends) are 64-bits.
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if (is64Bit && TM.getCodeModel() != CodeModel::Small)
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// Also, base and index reg must be 0 in order to use rip as base.
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if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
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AM.Base.Reg.Val || AM.IndexReg.Val))
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break;
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if (AM.GV != 0 || AM.CP != 0 || AM.ES != 0 || AM.JT != -1)
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break;
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@ -672,39 +674,27 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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// been picked, we can't fit the result available in the register in the
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// addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
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if (!AlreadySelected || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
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bool isStatic = TM.getRelocationModel() == Reloc::Static;
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SDOperand N0 = N.getOperand(0);
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// Mac OS X X86-64 lower 4G address is not available.
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bool isAbs32 = !is64Bit ||
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(isStatic && Subtarget->hasLow4GUserSpaceAddress());
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
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GlobalValue *GV = G->getGlobal();
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if (isAbs32 || isRoot) {
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AM.GV = GV;
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AM.Disp += G->getOffset();
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AM.isRIPRel = !isAbs32;
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return false;
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}
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AM.GV = GV;
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AM.Disp += G->getOffset();
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AM.isRIPRel = is64Bit;
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return false;
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} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
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if (isAbs32 || isRoot) {
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AM.CP = CP->getConstVal();
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AM.Align = CP->getAlignment();
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AM.Disp += CP->getOffset();
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AM.isRIPRel = !isAbs32;
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return false;
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}
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AM.CP = CP->getConstVal();
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AM.Align = CP->getAlignment();
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AM.Disp += CP->getOffset();
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AM.isRIPRel = is64Bit;
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return false;
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} else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
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if (isAbs32 || isRoot) {
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AM.ES = S->getSymbol();
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AM.isRIPRel = !isAbs32;
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return false;
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}
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AM.ES = S->getSymbol();
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AM.isRIPRel = is64Bit;
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return false;
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} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
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if (isAbs32 || isRoot) {
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AM.JT = J->getIndex();
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AM.isRIPRel = !isAbs32;
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return false;
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}
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AM.JT = J->getIndex();
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AM.isRIPRel = is64Bit;
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return false;
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}
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}
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break;
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@ -719,7 +709,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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break;
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case ISD::SHL:
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if (AlreadySelected || AM.IndexReg.Val != 0 || AM.Scale != 1)
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if (AlreadySelected || AM.IndexReg.Val != 0 || AM.Scale != 1 || AM.isRIPRel)
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break;
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
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@ -759,7 +749,8 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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if (!AlreadySelected &&
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AM.BaseType == X86ISelAddressMode::RegBase &&
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AM.Base.Reg.Val == 0 &&
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AM.IndexReg.Val == 0) {
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AM.IndexReg.Val == 0 &&
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!AM.isRIPRel) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
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if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
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AM.Scale = unsigned(CN->getValue())-1;
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@ -834,6 +825,9 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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// Scale must not be used already.
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if (AM.IndexReg.Val != 0 || AM.Scale != 1) break;
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// Not when RIP is used as the base.
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if (AM.isRIPRel) break;
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ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
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ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
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@ -874,7 +868,7 @@ bool X86DAGToDAGISel::MatchAddressBase(SDOperand N, X86ISelAddressMode &AM,
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// Is the base register already occupied?
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if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
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// If so, check to see if the scale index register is set.
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if (AM.IndexReg.Val == 0) {
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if (AM.IndexReg.Val == 0 && !AM.isRIPRel) {
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AM.IndexReg = N;
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AM.Scale = 1;
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return false;
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@ -1125,16 +1125,16 @@ def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
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def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, tconstpool:$src)>,
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Requires<[SmallCode, HasLow4G, IsStatic]>;
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Requires<[SmallCode, IsStatic]>;
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def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, tjumptable:$src)>,
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Requires<[SmallCode, HasLow4G, IsStatic]>;
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Requires<[SmallCode, IsStatic]>;
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def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, tglobaladdr:$src)>,
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Requires<[SmallCode, HasLow4G, IsStatic]>;
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Requires<[SmallCode, IsStatic]>;
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def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, texternalsym:$src)>,
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Requires<[SmallCode, HasLow4G, IsStatic]>;
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Requires<[SmallCode, IsStatic]>;
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// Calls
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// Direct PC relative function call for small code model. 32-bit displacement
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@ -172,7 +172,6 @@ def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
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def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
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def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
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def In64BitMode : Predicate<"Subtarget->is64Bit()">;
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def HasLow4G : Predicate<"Subtarget->hasLow4GUserSpaceAddress()">;
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def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
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def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
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def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
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@ -228,7 +228,6 @@ X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
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// FIXME: this is a known good value for Yonah. How about others?
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, MaxInlineSizeThreshold(128)
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, Is64Bit(is64Bit)
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, HasLow4GUserAddress(true)
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, TargetType(isELF) { // Default to ELF unless otherwise specified.
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// Determine default and user specified characteristics
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@ -300,9 +299,6 @@ X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
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? X86Subtarget::Intel : X86Subtarget::ATT;
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}
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if (TargetType == isDarwin && Is64Bit)
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HasLow4GUserAddress = false;
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if (TargetType == isDarwin ||
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TargetType == isCygwin ||
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TargetType == isMingw ||
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@ -82,10 +82,6 @@ private:
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/// pointer size is 64 bit.
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bool Is64Bit;
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/// HasLow4GUserAddress - True if the low 4G user-space address is available.
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///
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bool HasLow4GUserAddress;
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public:
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enum {
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isELF, isCygwin, isDarwin, isWindows, isMingw
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@ -115,10 +111,6 @@ public:
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bool is64Bit() const { return Is64Bit; }
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/// hasLow4GUserSpaceAddress - True if lower 4G user-space address is
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/// available.
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bool hasLow4GUserSpaceAddress() const { return HasLow4GUserAddress; }
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PICStyle::Style getPICStyle() const { return PICStyle; }
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void setPICStyle(PICStyle::Style Style) { PICStyle = Style; }
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@ -1,36 +1,35 @@
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; RUN: llvm-upgrade < %s | llvm-as | llc -relocation-model=pic -mtriple=i386-linux-gnu | not grep -F .text
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; RUN: llvm-upgrade < %s | llvm-as | llc -relocation-model=pic -mtriple=i686-apple-darwin | not grep lea
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; RUN: llvm-as < %s | llc -relocation-model=pic -mtriple=i386-linux-gnu | not grep -F .text
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; RUN: llvm-as < %s | llc -relocation-model=pic -mtriple=i686-apple-darwin | not grep lea
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; RUN: llvm-as < %s | llc -relocation-model=pic -mtriple=i686-apple-darwin | grep add | count 2
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implementation ; Functions:
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declare void @_Z3bari(i32)
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declare void %_Z3bari( int )
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linkonce void %_Z3fooILi1EEvi(int %Y) {
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define linkonce void @_Z3fooILi1EEvi(i32 %Y) {
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entry:
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%Y_addr = alloca int ; <int*> [#uses=2]
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"alloca point" = cast int 0 to int ; <int> [#uses=0]
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store int %Y, int* %Y_addr
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%tmp = load int* %Y_addr ; <int> [#uses=1]
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switch int %tmp, label %bb10 [
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int 0, label %bb3
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int 1, label %bb
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int 2, label %bb
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int 3, label %bb
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int 4, label %bb
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int 5, label %bb
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int 6, label %bb
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int 7, label %bb
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int 8, label %bb
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int 9, label %bb
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int 10, label %bb
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int 12, label %bb1
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int 13, label %bb5
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int 14, label %bb6
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int 16, label %bb2
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int 17, label %bb4
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int 23, label %bb8
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int 27, label %bb7
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int 34, label %bb9
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%Y_addr = alloca i32 ; <i32*> [#uses=2]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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store i32 %Y, i32* %Y_addr
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%tmp = load i32* %Y_addr ; <i32> [#uses=1]
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switch i32 %tmp, label %bb10 [
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i32 0, label %bb3
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i32 1, label %bb
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i32 2, label %bb
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i32 3, label %bb
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i32 4, label %bb
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i32 5, label %bb
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i32 6, label %bb
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i32 7, label %bb
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i32 8, label %bb
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i32 9, label %bb
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i32 10, label %bb
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i32 12, label %bb1
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i32 13, label %bb5
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i32 14, label %bb6
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i32 16, label %bb2
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i32 17, label %bb4
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i32 23, label %bb8
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i32 27, label %bb7
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i32 34, label %bb9
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]
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bb: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry
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@ -40,7 +39,7 @@ bb1: ; preds = %bb, %entry
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br label %bb2
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bb2: ; preds = %bb1, %entry
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call void %_Z3bari( int 1 )
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call void @_Z3bari( i32 1 )
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br label %bb11
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bb3: ; preds = %entry
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@ -53,7 +52,7 @@ bb5: ; preds = %bb4, %entry
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br label %bb6
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bb6: ; preds = %bb5, %entry
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call void %_Z3bari( int 2 )
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call void @_Z3bari( i32 2 )
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br label %bb11
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bb7: ; preds = %entry
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@ -63,7 +62,7 @@ bb8: ; preds = %bb7, %entry
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br label %bb9
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bb9: ; preds = %bb8, %entry
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call void %_Z3bari( int 3 )
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call void @_Z3bari( i32 3 )
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br label %bb11
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bb10: ; preds = %entry
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14
test/CodeGen/X86/x86-64-gv-offset.ll
Normal file
14
test/CodeGen/X86/x86-64-gv-offset.ll
Normal file
@ -0,0 +1,14 @@
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; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | not grep lea
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%struct.x = type { float, double }
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@X = global %struct.x { float 1.000000e+00, double 2.000000e+00 }, align 16 ; <%struct.x*> [#uses=2]
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define i32 @main() nounwind {
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entry:
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%tmp2 = load float* getelementptr (%struct.x* @X, i32 0, i32 0), align 16 ; <float> [#uses=1]
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%tmp4 = load double* getelementptr (%struct.x* @X, i32 0, i32 1), align 8 ; <double> [#uses=1]
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tail call void @t( float %tmp2, double %tmp4 ) nounwind
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ret i32 0
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}
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declare void @t(float, double)
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