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Intel syntax. Support .intel_syntax directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149270 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -34,7 +34,7 @@ struct X86Operand;
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class X86AsmParser : public MCTargetAsmParser {
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MCSubtargetInfo &STI;
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MCAsmParser &Parser;
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bool IntelSyntax;
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private:
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MCAsmParser &getParser() const { return Parser; }
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@ -94,7 +94,7 @@ private:
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public:
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X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
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: MCTargetAsmParser(), STI(sti), Parser(parser) {
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: MCTargetAsmParser(), STI(sti), Parser(parser), IntelSyntax(false) {
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// Initialize the set of available features.
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setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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@ -105,6 +105,10 @@ public:
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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virtual bool ParseDirective(AsmToken DirectiveID);
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bool isParsingIntelSyntax() {
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return IntelSyntax || getParser().getAssemblerDialect();
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}
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};
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} // end anonymous namespace
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@ -470,8 +474,7 @@ bool X86AsmParser::isDstOp(X86Operand &Op) {
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bool X86AsmParser::ParseRegister(unsigned &RegNo,
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SMLoc &StartLoc, SMLoc &EndLoc) {
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RegNo = 0;
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bool IntelSyntax = getParser().getAssemblerDialect();
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if (!IntelSyntax) {
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if (!isParsingIntelSyntax()) {
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const AsmToken &TokPercent = Parser.getTok();
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assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
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StartLoc = TokPercent.getLoc();
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@ -480,7 +483,7 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo,
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const AsmToken &Tok = Parser.getTok();
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if (Tok.isNot(AsmToken::Identifier)) {
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if (IntelSyntax) return true;
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if (isParsingIntelSyntax()) return true;
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return Error(StartLoc, "invalid register name",
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SMRange(StartLoc, Tok.getEndLoc()));
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}
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@ -564,7 +567,7 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo,
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}
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if (RegNo == 0) {
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if (IntelSyntax) return true;
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if (isParsingIntelSyntax()) return true;
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return Error(StartLoc, "invalid register name",
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SMRange(StartLoc, Tok.getEndLoc()));
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}
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@ -575,7 +578,7 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo,
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}
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X86Operand *X86AsmParser::ParseOperand() {
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if (getParser().getAssemblerDialect())
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if (isParsingIntelSyntax())
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return ParseIntelOperand();
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return ParseATTOperand();
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}
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@ -1170,7 +1173,7 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
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Name.startswith("rcl") || Name.startswith("rcr") ||
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Name.startswith("rol") || Name.startswith("ror")) &&
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Operands.size() == 3) {
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if (getParser().getAssemblerDialect()) {
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if (isParsingIntelSyntax()) {
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// Intel syntax
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X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]);
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if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
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@ -1486,7 +1489,7 @@ MatchAndEmitInstruction(SMLoc IDLoc,
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// First, try a direct match.
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switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo,
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getParser().getAssemblerDialect())) {
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isParsingIntelSyntax())) {
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default: break;
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case Match_Success:
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// Some instructions need post-processing to, for example, tweak which
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@ -1640,6 +1643,17 @@ bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
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return ParseDirectiveWord(2, DirectiveID.getLoc());
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else if (IDVal.startswith(".code"))
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return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
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else if (IDVal.startswith(".intel_syntax")) {
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IntelSyntax = true;
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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if(Parser.getTok().getString() == "noprefix") {
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// FIXME : Handle noprefix
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Parser.Lex();
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} else
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return true;
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}
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return false;
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}
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return true;
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}
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7
test/MC/X86/intel-syntax-2.s
Normal file
7
test/MC/X86/intel-syntax-2.s
Normal file
@ -0,0 +1,7 @@
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// RUN: llvm-mc -triple x86_64-unknown-unknown %s | FileCheck %s
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.intel_syntax
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_test:
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// CHECK: movl $257, -4(%rsp)
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mov DWORD PTR [RSP - 4], 257
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