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https://github.com/c64scene-ar/llvm-6502.git
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[AArch64] Use CHECK-LABEL in ARM64 ABI unit tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213703 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1,4 +1,4 @@
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; RUN: llc < %s -debug -march=arm64 -mcpu=cyclone -enable-misched=false | FileCheck %s
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; RUN: llc < %s -march=arm64 -mcpu=cyclone -enable-misched=false | FileCheck %s
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; RUN: llc < %s -O0 | FileCheck -check-prefix=FAST %s
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; REQUIRES: asserts
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target triple = "arm64-apple-darwin"
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@ -42,7 +42,7 @@ entry:
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define i32 @i8i16caller() nounwind readnone {
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entry:
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; CHECK: i8i16caller
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; CHECK-LABEL: i8i16caller
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; The 8th, 9th, 10th and 11th arguments are passed at sp, sp+2, sp+4, sp+5.
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; They are i8, i16, i8 and i8.
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; CHECK-DAG: strb {{w[0-9]+}}, [sp, #5]
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@ -50,7 +50,7 @@ entry:
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; CHECK-DAG: strh {{w[0-9]+}}, [sp, #2]
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; CHECK-DAG: strb {{w[0-9]+}}, [sp]
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; CHECK: bl
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; FAST: i8i16caller
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; FAST-LABEL: i8i16caller
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; FAST: strb {{w[0-9]+}}, [sp]
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; FAST: strh {{w[0-9]+}}, [sp, #2]
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; FAST: strb {{w[0-9]+}}, [sp, #4]
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@ -64,7 +64,7 @@ entry:
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; rdar://12651543
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define double @circle_center([2 x float] %a) nounwind ssp {
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%call = tail call double @ext([2 x float] %a) nounwind
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; CHECK: circle_center
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; CHECK-LABEL: circle_center
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; CHECK: bl
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ret double %call
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}
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@ -75,9 +75,9 @@ declare double @ext([2 x float])
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; A double argument will be passed on stack, so vecotr should be at sp+16.
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define double @fixed_4i(<4 x i32>* nocapture %in) nounwind {
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entry:
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; CHECK: fixed_4i
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; CHECK-LABEL: fixed_4i
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; CHECK: str [[REG_1:q[0-9]+]], [sp, #16]
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; FAST: fixed_4i
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; FAST-LABEL: fixed_4i
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; FAST: sub sp, sp, #64
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; FAST: mov x[[ADDR:[0-9]+]], sp
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; FAST: str [[REG_1:q[0-9]+]], [x[[ADDR]], #16]
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@ -93,7 +93,7 @@ declare double @args_vec_4i(double, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>,
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define void @test1(float %f1, double %d1, double %d2, double %d3, double %d4,
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double %d5, double %d6, double %d7, double %d8, i32 %i) nounwind ssp {
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entry:
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; CHECK: test1
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; CHECK-LABEL: test1
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; CHECK: ldr [[REG_1:d[0-9]+]], [sp]
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; CHECK: scvtf [[REG_2:s[0-9]+]], w0
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; CHECK: fadd s0, [[REG_2]], s0
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@ -110,7 +110,7 @@ entry:
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define void @test2(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6,
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i32 %i7, i32 %i8, i32 %i9, float %d1) nounwind ssp {
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entry:
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; CHECK: test2
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; CHECK-LABEL: test2
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; CHECK: scvtf [[REG_2:s[0-9]+]], w0
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; CHECK: fadd s0, [[REG_2]], s0
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; CHECK: ldr [[REG_1:s[0-9]+]], [sp]
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@ -129,9 +129,9 @@ entry:
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; Check alignment on stack for v64, f64, i64, f32, i32.
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define double @test3(<2 x i32>* nocapture %in) nounwind {
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entry:
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; CHECK: test3
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; CHECK-LABEL: test3
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; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]
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; FAST: test3
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; FAST-LABEL: test3
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; FAST: sub sp, sp, #32
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; FAST: mov x[[ADDR:[0-9]+]], sp
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; FAST: str [[REG_1:d[0-9]+]], [x[[ADDR]], #8]
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@ -146,7 +146,7 @@ declare double @args_vec_2i(double, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>,
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define double @test4(double* nocapture %in) nounwind {
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entry:
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; CHECK: test4
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; CHECK-LABEL: test4
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; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]
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; CHECK: str [[REG_2:w[0-9]+]], [sp]
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; CHECK: orr w0, wzr, #0x3
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@ -161,7 +161,7 @@ declare double @args_f64(double, double, double, double, double, double, double,
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define i64 @test5(i64* nocapture %in) nounwind {
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entry:
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; CHECK: test5
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; CHECK-LABEL: test5
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; CHECK: strb [[REG_3:w[0-9]+]], [sp, #16]
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; CHECK: str [[REG_1:x[0-9]+]], [sp, #8]
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; CHECK: str [[REG_2:w[0-9]+]], [sp]
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@ -175,7 +175,7 @@ declare i64 @args_i64(i64, i64, i64, i64, i64, i64, i64, i64, i32, i64,
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define i32 @test6(float* nocapture %in) nounwind {
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entry:
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; CHECK: test6
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; CHECK-LABEL: test6
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; CHECK: strb [[REG_2:w[0-9]+]], [sp, #8]
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; CHECK: str [[REG_1:s[0-9]+]], [sp, #4]
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; CHECK: strh [[REG_3:w[0-9]+]], [sp]
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@ -192,7 +192,7 @@ declare i32 @args_f32(i32, i32, i32, i32, i32, i32, i32, i32,
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define i32 @test7(i32* nocapture %in) nounwind {
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entry:
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; CHECK: test7
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; CHECK-LABEL: test7
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; CHECK: strb [[REG_2:w[0-9]+]], [sp, #8]
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; CHECK: str [[REG_1:w[0-9]+]], [sp, #4]
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; CHECK: strh [[REG_3:w[0-9]+]], [sp]
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@ -206,13 +206,13 @@ declare i32 @args_i32(i32, i32, i32, i32, i32, i32, i32, i32, i16 signext, i32,
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define i32 @test8(i32 %argc, i8** nocapture %argv) nounwind {
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entry:
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; CHECK: test8
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; CHECK-LABEL: test8
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; CHECK: strb {{w[0-9]+}}, [sp, #3]
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; CHECK: strb wzr, [sp, #2]
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; CHECK: strb {{w[0-9]+}}, [sp, #1]
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; CHECK: strb wzr, [sp]
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; CHECK: bl
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; FAST: test8
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; FAST-LABEL: test8
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; FAST: strb {{w[0-9]+}}, [sp]
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; FAST: strb {{w[0-9]+}}, [sp, #1]
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; FAST: strb {{w[0-9]+}}, [sp, #2]
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@ -34,7 +34,7 @@ target triple = "arm64-apple-darwin"
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; structs with size < 8 bytes, passed via i64 in x1 and x2
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define i32 @f38(i32 %i, i64 %s1.coerce, i64 %s2.coerce) #0 {
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entry:
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; CHECK: f38
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; CHECK-LABEL: f38
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; CHECK: add w[[A:[0-9]+]], w1, w0
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; CHECK: add {{w[0-9]+}}, w[[A]], w2
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%s1.sroa.0.0.extract.trunc = trunc i64 %s1.coerce to i32
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@ -56,7 +56,7 @@ entry:
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define i32 @caller38() #1 {
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entry:
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; CHECK: caller38
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; CHECK-LABEL: caller38
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; CHECK: ldr x1,
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; CHECK: ldr x2,
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%0 = load i64* bitcast (%struct.s38* @g38 to i64*), align 4
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@ -72,7 +72,7 @@ declare i32 @f38_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6,
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; i9 at [sp]
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define i32 @caller38_stack() #1 {
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entry:
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; CHECK: caller38_stack
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; CHECK-LABEL: caller38_stack
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; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8]
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; CHECK: movz w[[C:[0-9]+]], #0x9
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; CHECK: str w[[C]], [sp]
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@ -87,7 +87,7 @@ entry:
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; passed via i128 in x1 and x3
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define i32 @f39(i32 %i, i128 %s1.coerce, i128 %s2.coerce) #0 {
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entry:
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; CHECK: f39
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; CHECK-LABEL: f39
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; CHECK: add w[[A:[0-9]+]], w1, w0
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; CHECK: add {{w[0-9]+}}, w[[A]], w3
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%s1.sroa.0.0.extract.trunc = trunc i128 %s1.coerce to i32
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@ -109,7 +109,7 @@ entry:
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define i32 @caller39() #1 {
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entry:
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; CHECK: caller39
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; CHECK-LABEL: caller39
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; CHECK: ldp x1, x2,
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; CHECK: ldp x3, x4,
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%0 = load i128* bitcast (%struct.s39* @g39 to i128*), align 16
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@ -125,7 +125,7 @@ declare i32 @f39_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6,
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; passed on stack at [sp+16] and [sp+32]
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define i32 @caller39_stack() #1 {
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entry:
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; CHECK: caller39_stack
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; CHECK-LABEL: caller39_stack
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; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #32]
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; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
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; CHECK: movz w[[C:[0-9]+]], #0x9
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@ -141,7 +141,7 @@ entry:
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; passed via i128 in x1 and x3
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define i32 @f40(i32 %i, [2 x i64] %s1.coerce, [2 x i64] %s2.coerce) #0 {
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entry:
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; CHECK: f40
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; CHECK-LABEL: f40
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; CHECK: add w[[A:[0-9]+]], w1, w0
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; CHECK: add {{w[0-9]+}}, w[[A]], w3
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%s1.coerce.fca.0.extract = extractvalue [2 x i64] %s1.coerce, 0
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@ -165,7 +165,7 @@ entry:
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define i32 @caller40() #1 {
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entry:
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; CHECK: caller40
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; CHECK-LABEL: caller40
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; CHECK: ldp x1, x2,
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; CHECK: ldp x3, x4,
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%0 = load [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4
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@ -181,7 +181,7 @@ declare i32 @f40_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6,
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; passed on stack at [sp+8] and [sp+24]
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define i32 @caller40_stack() #1 {
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entry:
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; CHECK: caller40_stack
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; CHECK-LABEL: caller40_stack
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; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #24]
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; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8]
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; CHECK: movz w[[C:[0-9]+]], #0x9
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@ -197,7 +197,7 @@ entry:
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; passed via i128 in x1 and x3
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define i32 @f41(i32 %i, i128 %s1.coerce, i128 %s2.coerce) #0 {
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entry:
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; CHECK: f41
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; CHECK-LABEL: f41
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; CHECK: add w[[A:[0-9]+]], w1, w0
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; CHECK: add {{w[0-9]+}}, w[[A]], w3
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%s1.sroa.0.0.extract.trunc = trunc i128 %s1.coerce to i32
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@ -219,7 +219,7 @@ entry:
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define i32 @caller41() #1 {
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entry:
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; CHECK: caller41
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; CHECK-LABEL: caller41
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; CHECK: ldp x1, x2,
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; CHECK: ldp x3, x4,
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%0 = load i128* bitcast (%struct.s41* @g41 to i128*), align 16
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@ -235,7 +235,7 @@ declare i32 @f41_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6,
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; passed on stack at [sp+16] and [sp+32]
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define i32 @caller41_stack() #1 {
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entry:
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; CHECK: caller41_stack
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; CHECK-LABEL: caller41_stack
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; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #32]
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; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
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; CHECK: movz w[[C:[0-9]+]], #0x9
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@ -250,7 +250,7 @@ entry:
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; structs with size of 22 bytes, passed indirectly in x1 and x2
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define i32 @f42(i32 %i, %struct.s42* nocapture %s1, %struct.s42* nocapture %s2) #2 {
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entry:
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; CHECK: f42
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; CHECK-LABEL: f42
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; CHECK: ldr w[[A:[0-9]+]], [x1]
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; CHECK: ldr w[[B:[0-9]+]], [x2]
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; CHECK: add w[[C:[0-9]+]], w[[A]], w0
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@ -280,7 +280,7 @@ entry:
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; For s1, we allocate a 22-byte space, pass its address via x1
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define i32 @caller42() #3 {
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entry:
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; CHECK: caller42
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; CHECK-LABEL: caller42
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; CHECK: str {{x[0-9]+}}, [sp, #48]
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; CHECK: str {{q[0-9]+}}, [sp, #32]
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; CHECK: str {{x[0-9]+}}, [sp, #16]
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@ -290,7 +290,7 @@ entry:
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; Space for s1 is allocated at sp+32
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; Space for s2 is allocated at sp
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; FAST: caller42
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; FAST-LABEL: caller42
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; FAST: sub sp, sp, #96
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; Space for s1 is allocated at fp-24 = sp+72
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; Space for s2 is allocated at sp+48
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@ -316,7 +316,7 @@ declare i32 @f42_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6,
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define i32 @caller42_stack() #3 {
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entry:
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; CHECK: caller42_stack
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; CHECK-LABEL: caller42_stack
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; CHECK: mov x29, sp
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; CHECK: sub sp, sp, #96
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; CHECK: stur {{x[0-9]+}}, [x29, #-16]
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@ -333,7 +333,7 @@ entry:
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; CHECK: movz w[[C:[0-9]+]], #0x9
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; CHECK: str w[[C]], [sp]
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; FAST: caller42_stack
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; FAST-LABEL: caller42_stack
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; Space for s1 is allocated at fp-24
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; Space for s2 is allocated at fp-48
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; FAST: sub x[[A:[0-9]+]], x29, #24
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@ -359,12 +359,12 @@ entry:
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; passed indirectly in x1 and x2
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define i32 @f43(i32 %i, %struct.s43* nocapture %s1, %struct.s43* nocapture %s2) #2 {
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entry:
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; CHECK: f43
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; CHECK-LABEL: f43
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; CHECK: ldr w[[A:[0-9]+]], [x1]
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; CHECK: ldr w[[B:[0-9]+]], [x2]
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; CHECK: add w[[C:[0-9]+]], w[[A]], w0
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; CHECK: add {{w[0-9]+}}, w[[C]], w[[B]]
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; FAST: f43
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; FAST-LABEL: f43
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; FAST: ldr w[[A:[0-9]+]], [x1]
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; FAST: ldr w[[B:[0-9]+]], [x2]
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; FAST: add w[[C:[0-9]+]], w[[A]], w0
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@ -388,7 +388,7 @@ entry:
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define i32 @caller43() #3 {
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entry:
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; CHECK: caller43
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; CHECK-LABEL: caller43
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; CHECK: str {{q[0-9]+}}, [sp, #48]
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; CHECK: str {{q[0-9]+}}, [sp, #32]
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; CHECK: str {{q[0-9]+}}, [sp, #16]
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@ -398,7 +398,7 @@ entry:
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; Space for s1 is allocated at sp+32
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; Space for s2 is allocated at sp
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; FAST: caller43
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; FAST-LABEL: caller43
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; FAST: mov x29, sp
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; Space for s1 is allocated at sp+32
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; Space for s2 is allocated at sp
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@ -428,7 +428,7 @@ declare i32 @f43_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6,
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define i32 @caller43_stack() #3 {
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entry:
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; CHECK: caller43_stack
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; CHECK-LABEL: caller43_stack
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; CHECK: mov x29, sp
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; CHECK: sub sp, sp, #96
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; CHECK: stur {{q[0-9]+}}, [x29, #-16]
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@ -445,7 +445,7 @@ entry:
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; CHECK: movz w[[C:[0-9]+]], #0x9
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; CHECK: str w[[C]], [sp]
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; FAST: caller43_stack
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; FAST-LABEL: caller43_stack
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; FAST: sub sp, sp, #96
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; Space for s1 is allocated at fp-32 = sp+64
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; Space for s2 is allocated at sp+32
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@ -481,12 +481,12 @@ declare i32 @callee_i128_split(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5,
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define i32 @i128_split() {
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entry:
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; CHECK: i128_split
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; CHECK-LABEL: i128_split
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; "i128 %0" should be on stack at [sp].
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; "i32 8" should be on stack at [sp, #16].
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; CHECK: str {{w[0-9]+}}, [sp, #16]
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; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp]
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; FAST: i128_split
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; FAST-LABEL: i128_split
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; FAST: sub sp, sp, #48
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; FAST: mov x[[ADDR:[0-9]+]], sp
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; FAST: str {{w[0-9]+}}, [x[[ADDR]], #16]
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@ -504,12 +504,12 @@ declare i32 @callee_i64(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5,
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define i32 @i64_split() {
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entry:
|
||||
; CHECK: i64_split
|
||||
; CHECK-LABEL: i64_split
|
||||
; "i64 %0" should be in register x7.
|
||||
; "i32 8" should be on stack at [sp].
|
||||
; CHECK: ldr x7, [{{x[0-9]+}}]
|
||||
; CHECK: str {{w[0-9]+}}, [sp]
|
||||
; FAST: i64_split
|
||||
; FAST-LABEL: i64_split
|
||||
; FAST: ldr x7, [{{x[0-9]+}}]
|
||||
; FAST: str {{w[0-9]+}}, [sp]
|
||||
%0 = load i64* bitcast (%struct.s41* @g41 to i64*), align 16
|
||||
|
Loading…
Reference in New Issue
Block a user