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Add braces for legibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115043 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -289,7 +289,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue N,
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}
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// Match simple R +/- imm12 operands.
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if (N.getOpcode() == ISD::ADD)
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if (N.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if ((RHSC >= 0 && RHSC < 0x1000) ||
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@ -312,6 +312,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue N,
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return true;
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}
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}
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}
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// Otherwise this is R +/- [possibly shifted] R.
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ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
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