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[X86] Fix wrong target specific combine on SETCC nodes.
Part of the folding logic implemented by function 'PerformISDSETCCCombine' only worked under the assumption that the condition code in input could have been either SETNE or SETEQ. Unfortunately that assumption was incorrect, and in some cases the algorithm ended up incorrectly folding SETCC nodes. The incorrect folding only affected SETCC dag nodes where: - one of the operands was a build_vector of all zeroes; - the other operand was a SIGN_EXTEND from a vector of MVT:i1 elements; - the condition code was neither SETNE nor SETEQ. Example: (setcc (v4i32 (sign_extend v4i1:%A)), (v4i32 VectorOfAllZeroes), setge) Before this patch, the entire dag node sequence from the example was incorrectly folded to node %A. With this patch, the dag node sequence is folded to a (xor %A, (v4i1 VectorOfAllOnes)). Added test setcc-combine.ll. Thanks to Greg Bedwell for spotting this issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232046 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
parent
b4c1547749
commit
be9322ae7c
@ -23178,45 +23178,51 @@ static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
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if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
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if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
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SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
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LHS.getValueType(), RHS, LHS.getOperand(1));
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return DAG.getSetCC(SDLoc(N), N->getValueType(0),
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addV, DAG.getConstant(0, addV.getValueType()), CC);
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SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N), LHS.getValueType(), RHS,
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LHS.getOperand(1));
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return DAG.getSetCC(SDLoc(N), N->getValueType(0), addV,
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DAG.getConstant(0, addV.getValueType()), CC);
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}
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if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
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if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
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SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
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RHS.getValueType(), LHS, RHS.getOperand(1));
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return DAG.getSetCC(SDLoc(N), N->getValueType(0),
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addV, DAG.getConstant(0, addV.getValueType()), CC);
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SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N), RHS.getValueType(), LHS,
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RHS.getOperand(1));
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return DAG.getSetCC(SDLoc(N), N->getValueType(0), addV,
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DAG.getConstant(0, addV.getValueType()), CC);
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}
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if (VT.getScalarType() == MVT::i1) {
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bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
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(LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
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bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
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if (!IsSEXT0 && !IsVZero0)
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return SDValue();
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bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
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(RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
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if (VT.getScalarType() == MVT::i1 &&
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(CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
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bool IsSEXT0 =
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(LHS.getOpcode() == ISD::SIGN_EXTEND) &&
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(LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
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bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
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if (!IsSEXT1 && !IsVZero1)
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return SDValue();
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if (!IsSEXT0 || !IsVZero1) {
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// Swap the operands and update the condition code.
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std::swap(LHS, RHS);
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CC = ISD::getSetCCSwappedOperands(CC);
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IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
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(LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
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IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
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}
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if (IsSEXT0 && IsVZero1) {
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assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
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if (CC == ISD::SETEQ)
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assert(VT == LHS.getOperand(0).getValueType() &&
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"Uexpected operand type");
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if (CC == ISD::SETGT)
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return DAG.getConstant(0, VT);
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if (CC == ISD::SETLE)
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return DAG.getConstant(1, VT);
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if (CC == ISD::SETEQ || CC == ISD::SETGE)
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return DAG.getNOT(DL, LHS.getOperand(0), VT);
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assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
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"Unexpected condition code!");
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return LHS.getOperand(0);
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}
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if (IsSEXT1 && IsVZero0) {
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assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
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if (CC == ISD::SETEQ)
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return DAG.getNOT(DL, RHS.getOperand(0), VT);
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return RHS.getOperand(0);
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}
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}
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return SDValue();
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166
test/CodeGen/X86/setcc-combine.ll
Normal file
166
test/CodeGen/X86/setcc-combine.ll
Normal file
@ -0,0 +1,166 @@
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; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic < %s | FileCheck %s
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define i32 @test_eq_1(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_eq_1:
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; CHECK: pcmpgtd %xmm0, %xmm1
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; CHECK-NEXT: pxor {{.*}}(%rip), %xmm1
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; CHECK: retq
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entry:
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%cmp = icmp slt <4 x i32> %A, %B
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp eq <4 x i32> %sext, zeroinitializer
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%0 = extractelement <4 x i1> %cmp1, i32 1
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i32 @test_ne_1(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_ne_1:
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; CHECK: pcmpgtd %xmm0, %xmm1
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; CHECK-NOT: pxor
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; CHECK: retq
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entry:
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%cmp = icmp slt <4 x i32> %A, %B
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp ne <4 x i32> %sext, zeroinitializer
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%0 = extractelement <4 x i1> %cmp1, i32 1
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i32 @test_le_1(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_le_1:
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; CHECK: movl $-1, %eax
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; CHECK-NEXT: retq
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entry:
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%cmp = icmp slt <4 x i32> %A, %B
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp sle <4 x i32> %sext, zeroinitializer
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%0 = extractelement <4 x i1> %cmp1, i32 1
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i32 @test_ge_1(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_ge_1:
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; CHECK: pcmpgtd %xmm0, %xmm1
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; CHECK: pxor {{.*}}(%rip), %xmm1
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; CHECK: retq
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entry:
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%cmp = icmp slt <4 x i32> %A, %B
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp sge <4 x i32> %sext, zeroinitializer
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%0 = extractelement <4 x i1> %cmp1, i32 1
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i32 @test_lt_1(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_lt_1:
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; CHECK: pcmpgtd %xmm0, %xmm1
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; CHECK-NOT: pxor
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; CHECK: retq
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entry:
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%cmp = icmp slt <4 x i32> %A, %B
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp slt <4 x i32> %sext, zeroinitializer
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%0 = extractelement <4 x i1> %cmp, i32 1
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i32 @test_gt_1(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_gt_1:
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; CHECK: xorl %eax, %eax
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; CHECK: retq
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entry:
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%cmp = icmp slt <4 x i32> %A, %B
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp sgt <4 x i32> %sext, zeroinitializer
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%0 = extractelement <4 x i1> %cmp1, i32 1
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i32 @test_eq_2(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_eq_2:
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; CHECK: pcmpgtd %xmm1, %xmm0
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; CHECK-NEXT: pxor {{.*}}(%rip), %xmm0
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; CHECK: retq
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entry:
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%cmp = icmp slt <4 x i32> %B, %A
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp eq <4 x i32> %sext, zeroinitializer
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%0 = extractelement <4 x i1> %cmp1, i32 1
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i32 @test_ne_2(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_ne_2:
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; CHECK: pcmpgtd %xmm1, %xmm0
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; CHECK-NOT: pxor
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; CHECK: retq
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entry:
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%cmp = icmp slt <4 x i32> %B, %A
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp ne <4 x i32> %sext, zeroinitializer
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%0 = extractelement <4 x i1> %cmp1, i32 1
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i32 @test_le_2(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_le_2:
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; CHECK: pcmpgtd %xmm1, %xmm0
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; CHECK: pxor {{.*}}(%rip), %xmm0
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; CHECK: retq
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entry:
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%cmp = icmp slt <4 x i32> %B, %A
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp sle <4 x i32> zeroinitializer, %sext
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%0 = extractelement <4 x i1> %cmp1, i32 1
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i32 @test_ge_2(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_ge_2:
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; CHECK: movl $-1, %eax
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; CHECK: retq
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entry:
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%cmp = icmp slt <4 x i32> %B, %A
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp sge <4 x i32> zeroinitializer, %sext
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%0 = extractelement <4 x i1> %cmp1, i32 1
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i32 @test_lt_2(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_lt_2:
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; CHECK: pcmpgtd %xmm1, %xmm0
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; CHECK-NOT: pxor
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; CHECK: retq
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entry:
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%cmp = icmp slt <4 x i32> %B, %A
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp slt <4 x i32> zeroinitializer, %sext
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%0 = extractelement <4 x i1> %cmp, i32 1
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i32 @test_gt_2(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_gt_2:
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; CHECK: pcmpgtd %xmm1, %xmm0
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; CHECK-NOT: pxor
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; CHECK: retq
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entry:
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%cmp = icmp slt <4 x i32> %B, %A
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp sgt <4 x i32> zeroinitializer, %sext
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%0 = extractelement <4 x i1> %cmp1, i32 1
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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