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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-18 12:29:21 +00:00
remove RET hack, add proper support for rets (watching out for ret voids)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25486 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -585,57 +585,6 @@ SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
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getI64Imm(Amt), Select(N->getOperand(0)));
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}
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case ISD::RET: {
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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SDOperand InFlag;
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switch (N->getNumOperands()) {
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default:
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assert(0 && "Unknown return instruction!");
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case 2: {
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SDOperand RetVal = Select(N->getOperand(1));
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switch (RetVal.getValueType()) {
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default: assert(0 && "I don't know how to return this type! (promote?)");
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// FIXME: do I need to add support for bools here?
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// (return '0' or '1' in r8, basically...)
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//
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// FIXME: need to round floats - 80 bits is bad, the tester
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// told me so
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case MVT::i64:
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// we mark r8 as live on exit up above in LowerArguments()
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// BuildMI(BB, IA64::MOV, 1, IA64::r8).addReg(Tmp1);
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Chain = CurDAG->getCopyToReg(Chain, IA64::r8, RetVal);
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InFlag = Chain.getValue(1);
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break;
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case MVT::f64:
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// we mark F8 as live on exit up above in LowerArguments()
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// BuildMI(BB, IA64::FMOV, 1, IA64::F8).addReg(Tmp1);
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Chain = CurDAG->getCopyToReg(Chain, IA64::F8, RetVal);
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InFlag = Chain.getValue(1);
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break;
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}
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break;
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}
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case 1:
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break;
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}
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// we need to copy VirtGPR (the vreg (to become a real reg)) that holds
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// the output of this function's alloc instruction back into ar.pfs
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// before we return. this copy must not float up above the last
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// outgoing call in this function!!!
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SDOperand AR_PFSVal = CurDAG->getCopyFromReg(Chain, IA64Lowering.VirtGPR,
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MVT::i64);
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Chain = AR_PFSVal.getValue(1);
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Chain = CurDAG->getCopyToReg(Chain, IA64::AR_PFS, AR_PFSVal);
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// and then just emit a 'ret' instruction
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// before returning, restore the ar.pfs register (set by the 'alloc' up top)
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// BuildMI(BB, IA64::MOV, 1).addReg(IA64::AR_PFS).addReg(IA64Lowering.VirtGPR);
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//
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return CurDAG->SelectNodeTo(N, IA64::RET, MVT::Other, Chain);
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}
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case ISD::BR:
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// FIXME: we don't need long branches all the time!
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return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
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@ -39,6 +39,11 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
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setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
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// We need to handle ISD::RET for void functions ourselves,
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// so we get a chance to restore ar.pfs before adding a
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// br.ret insn
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setSetCCResultType(MVT::i1);
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setShiftAmountType(MVT::i64);
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@ -101,6 +106,7 @@ const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
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default: return 0;
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case IA64ISD::GETFD: return "IA64ISD::GETFD";
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case IA64ISD::BRCALL: return "IA64ISD::BRCALL";
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case IA64ISD::RET_FLAG: return "IA64ISD::RET_FLAG";
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}
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}
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@ -524,6 +530,44 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
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return std::make_pair(RetVal, Chain);
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}
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SDOperand IA64TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
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SelectionDAG &DAG) {
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SDOperand Copy, InFlag;
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SDOperand AR_PFSVal = DAG.getCopyFromReg(Chain, this->VirtGPR,
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MVT::i64);
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Chain = AR_PFSVal.getValue(1);
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switch (Op.getValueType()) {
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default: assert(0 && "Unknown type to return! (promote?)");
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case MVT::i64:
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Copy = DAG.getCopyToReg(Chain, IA64::r8, Op, InFlag);
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break;
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case MVT::f64:
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Copy = DAG.getCopyToReg(Chain, IA64::F8, Op, InFlag);
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break;
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}
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Chain = Copy.getValue(0);
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InFlag = Copy.getValue(1);
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// we need to copy VirtGPR (the vreg (to become a real reg)) that holds
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// the output of this function's alloc instruction back into ar.pfs
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// before we return. this copy must not float up above the last
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// outgoing call in this function - we flag this to the ret instruction
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Chain = DAG.getCopyToReg(Chain, IA64::AR_PFS, AR_PFSVal, InFlag);
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InFlag = Chain.getValue(1);
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// and then just emit a 'ret' instruction
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std::vector<MVT::ValueType> NodeTys;
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std::vector<SDOperand> RetOperands;
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NodeTys.push_back(MVT::Other);
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NodeTys.push_back(MVT::Flag);
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RetOperands.push_back(Chain);
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RetOperands.push_back(InFlag);
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return DAG.getNode(IA64ISD::RET_FLAG, NodeTys, RetOperands);
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// return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, MVT::Other, Copy, Chain, InFlag);
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}
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SDOperand
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IA64TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
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Value *VAListV, SelectionDAG &DAG) {
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@ -566,3 +610,25 @@ LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
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abort();
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}
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SDOperand IA64TargetLowering::
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LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default: assert(0 && "Should not custom lower this!");
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case ISD::RET: { // the DAGgy stuff takes care of
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// restoring ar.pfs before adding a br.ret for functions
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// that return something, but we need to take care of stuff
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// that returns void manually, so here it is:
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assert(Op.getNumOperands()==1 &&
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"trying to custom lower a return other than void! (numops!=1)");
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SDOperand Chain = Op.getOperand(0);
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SDOperand AR_PFSVal = DAG.getCopyFromReg(Chain, this->VirtGPR,
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MVT::i64);
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Chain = AR_PFSVal.getValue(1);
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Chain = DAG.getCopyToReg(Chain, IA64::AR_PFS, AR_PFSVal);
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// and then just emit a 'ret' instruction
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return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, Chain);
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}
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}
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}
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@ -30,7 +30,10 @@ namespace llvm {
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GETFD,
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// TODO: explain this hack
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BRCALL
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BRCALL,
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// RET_FLAG - Return with a flag operand
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RET_FLAG
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};
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}
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@ -64,9 +67,18 @@ namespace llvm {
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bool isTailCall, SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG);
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/// LowerReturnTo - This spits out restore-previous-frame-state+br.ret
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/// instructions
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virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
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SelectionDAG &DAG);
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/// LowerOperation - for custom lowering specific ops
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/// (currently, only "ret void")
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
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Value *VAListV, SelectionDAG &DAG);
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virtual std::pair<SDOperand,SDOperand>
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LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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const Type *ArgTy, SelectionDAG &DAG);
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@ -21,6 +21,10 @@ include "IA64InstrFormats.td"
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def IA64getfd : SDNode<"IA64ISD::GETFD", SDTFPToIntOp, []>;
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def SDT_IA64RetFlag : SDTypeProfile<0, 0, []>;
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def retflag : SDNode<"IA64ISD::RET_FLAG", SDT_IA64RetFlag,
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[SDNPHasChain, SDNPOptInFlag]>;
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//===---------
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def u2imm : Operand<i8>;
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@ -717,7 +721,9 @@ let isCall = 1, noResults = 1, /* isTerminator = 1, isBranch = 1, */
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"($qp) br.cond.call.sptk $dst;;">;
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}
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// Return branch:
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let isTerminator = 1, isReturn = 1, noResults = 1 in
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def RET : RawForm<0x03, 0xb0, (ops), "br.ret.sptk.many rp;;">; // return
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def RET : AForm_DAG<0x03, 0x0b, (ops),
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"br.ret.sptk.many rp;;",
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[(retflag)]>; // return
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def : Pat<(ret), (RET)>;
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