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Switch lowering: fix assert in buildBitTests (PR23738)
When checking (High - Low + 1).sle(BitWidth), BitWidth would be truncated to the size of the left-hand side. In the case of this PR, the left-hand side was i4, so BitWidth=64 got truncated to 0 and the assert failed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239048 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7614,7 +7614,8 @@ bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
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const int BitWidth =
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DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
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assert((High - Low + 1).sle(BitWidth) && "Case range must fit in bit mask!");
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uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
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assert(Range <= (uint64_t)BitWidth && "Case range must fit in bit mask!");
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if (Low.isNonNegative() && High.slt(BitWidth)) {
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// Optimize the case where all the case values fit in a
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@ -534,3 +534,18 @@ return: ret void
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; CHECK-NOT: cmpl
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; CHECK: cmpl $99
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}
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define void @pr23738(i4 %x) {
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entry:
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switch i4 %x, label %bb0 [
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i4 0, label %bb1
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i4 1, label %bb1
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i4 -5, label %bb1
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]
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bb0: tail call void @g(i32 0) br label %return
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bb1: tail call void @g(i32 1) br label %return
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return: ret void
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; Don't assert due to truncating the bitwidth (64) to i4 when checking
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; that the bit-test range fits in a word.
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}
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