6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-24 09:29:42 +00:00
Code Issues Projects Releases Wiki Activity

Switch lowering: fix assert in buildBitTests (PR23738)

Browse Source 
When checking (High - Low + 1).sle(BitWidth), BitWidth would be truncated
to the size of the left-hand side. In the case of this PR, the left-hand
side was i4, so BitWidth=64 got truncated to 0 and the assert failed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239048 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hans Wennborg 2015-06-04 15:55:00 +00:00
parent 9f299abc05
commit bebb0b5a34
2 changed files with 17 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -7614,7 +7614,8 @@ bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
const int BitWidth =
DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
assert((High - Low + 1).sle(BitWidth) && "Case range must fit in bit mask!");
uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
assert(Range <= (uint64_t)BitWidth && "Case range must fit in bit mask!");
if (Low.isNonNegative() && High.slt(BitWidth)) {
// Optimize the case where all the case values fit in a

15
test/CodeGen/X86/switch.ll
View File

@ -534,3 +534,18 @@ return: ret void
; CHECK-NOT: cmpl
; CHECK: cmpl $99
}
define void @pr23738(i4 %x) {
entry:
switch i4 %x, label %bb0 [
i4 0, label %bb1
i4 1, label %bb1
i4 -5, label %bb1
]
bb0: tail call void @g(i32 0) br label %return
bb1: tail call void @g(i32 1) br label %return
return: ret void
; Don't assert due to truncating the bitwidth (64) to i4 when checking
; that the bit-test range fits in a word.
}