mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 00:29:20 +00:00
Clean up ARM fused multiply + add/sub support some more: rename some isel
predicates. Also remove NEON2 since it's not really useful and it is confusing. If NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it really mean? rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -38,9 +38,6 @@ def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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"Enable NEON instructions",
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[FeatureVFP3]>;
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def FeatureNEON2 : SubtargetFeature<"neon2", "HasNEON2", "true",
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"Enable Advanced SIMD2 instructions",
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[FeatureNEON]>;
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def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
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"Enable Thumb2 instructions">;
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def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
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@ -728,7 +728,7 @@ void ARMAsmPrinter::emitAttributes() {
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if (Subtarget->hasNEON() && emitFPU) {
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/* NEON is not exactly a VFP architecture, but GAS emit one of
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* neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
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if (Subtarget->hasNEON2())
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if (Subtarget->hasVFP4())
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AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
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"neon-vfpv4");
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else
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@ -181,12 +181,8 @@ def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
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AssemblerPredicate<"FeatureVFP3">;
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def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
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AssemblerPredicate<"FeatureVFP4">;
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def NoVFP4 : Predicate<"!Subtarget->hasVFP4()">;
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def HasNEON : Predicate<"Subtarget->hasNEON()">,
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AssemblerPredicate<"FeatureNEON">;
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def HasNEON2 : Predicate<"Subtarget->hasNEON2()">,
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AssemblerPredicate<"FeatureNEON,FeatureVFP4">;
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def NoNEON2 : Predicate<"!Subtarget->hasNEON2()">;
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def HasFP16 : Predicate<"Subtarget->hasFP16()">,
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AssemblerPredicate<"FeatureFP16">;
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def HasDivide : Predicate<"Subtarget->hasDivide()">,
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@ -221,8 +217,10 @@ def UseMovt : Predicate<"Subtarget->useMovt()">;
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def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
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def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
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// Allow more precision in FP computation
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def FPContractions : Predicate<"!TM.Options.NoExcessFPPrecision">;
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// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
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// But only select them if more precision in FP computation is allowed.
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def UseFusedMAC : Predicate<"!TM.Options.NoExcessFPPrecision">;
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def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4()">;
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//===----------------------------------------------------------------------===//
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// ARM Flag Definitions.
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@ -4005,10 +4005,10 @@ defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
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IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
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def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
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v2f32, fmul_su, fadd_mlx>,
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Requires<[HasNEON, UseFPVMLx, NoNEON2]>;
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Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
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def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
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v4f32, fmul_su, fadd_mlx>,
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Requires<[HasNEON, UseFPVMLx, NoNEON2]>;
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Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
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defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
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IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
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def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
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@ -4063,10 +4063,10 @@ defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
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IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
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def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
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v2f32, fmul_su, fsub_mlx>,
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Requires<[HasNEON, UseFPVMLx, NoNEON2]>;
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Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
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def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
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v4f32, fmul_su, fsub_mlx>,
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Requires<[HasNEON, UseFPVMLx, NoNEON2]>;
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Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
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defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
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IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
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def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
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@ -4118,27 +4118,27 @@ defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
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// Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
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def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
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v2f32, fmul_su, fadd_mlx>,
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Requires<[HasNEON2,FPContractions]>;
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Requires<[HasVFP4,UseFusedMAC]>;
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def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
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v4f32, fmul_su, fadd_mlx>,
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Requires<[HasNEON2,FPContractions]>;
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Requires<[HasVFP4,UseFusedMAC]>;
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// Fused Vector Multiply Subtract (floating-point)
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def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
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v2f32, fmul_su, fsub_mlx>,
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Requires<[HasNEON2,FPContractions]>;
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Requires<[HasVFP4,UseFusedMAC]>;
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def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
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v4f32, fmul_su, fsub_mlx>,
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Requires<[HasNEON2,FPContractions]>;
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Requires<[HasVFP4,UseFusedMAC]>;
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// Match @llvm.fma.* intrinsics
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def : Pat<(fma (v2f32 DPR:$src1), (v2f32 DPR:$Vn), (v2f32 DPR:$Vm)),
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(VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
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Requires<[HasNEON2]>;
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Requires<[HasVFP4]>;
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def : Pat<(fma (v4f32 QPR:$src1), (v4f32 QPR:$Vn), (v4f32 QPR:$Vm)),
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(VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
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Requires<[HasNEON2]>;
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Requires<[HasVFP4]>;
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// Vector Subtract Operations.
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@ -5492,13 +5492,13 @@ def : N3VSPat<fadd, VADDfd>;
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def : N3VSPat<fsub, VSUBfd>;
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def : N3VSPat<fmul, VMULfd>;
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def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
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Requires<[HasNEON, UseNEONForFP, UseFPVMLx, NoNEON2]>;
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Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
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def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
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Requires<[HasNEON, UseNEONForFP, UseFPVMLx, NoNEON2]>;
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Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
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def : N3VSMulOpPat<fmul, fadd, VFMAfd>,
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Requires<[HasNEON2, UseNEONForFP, FPContractions]>;
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Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
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def : N3VSMulOpPat<fmul, fsub, VFMSfd>,
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Requires<[HasNEON2, UseNEONForFP, FPContractions]>;
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Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
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def : N2VSPat<fabs, VABSfd>;
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def : N2VSPat<fneg, VNEGfd>;
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def : N3VSPat<NEONfmax, VMAXfd>;
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@ -950,7 +950,7 @@ def VMLAD : ADbI<0b11100, 0b00, 0, 0,
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[(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">,
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Requires<[HasVFP2,UseFPVMLx,NoVFP4]>;
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Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
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def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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@ -958,7 +958,7 @@ def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
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[(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">,
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,NoVFP4]> {
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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@ -966,10 +966,10 @@ def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
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def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
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(VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
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Requires<[HasVFP2,UseFPVMLx,NoVFP4]>;
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Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
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def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
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(VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
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Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,NoVFP4]>;
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Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
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def VMLSD : ADbI<0b11100, 0b00, 1, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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@ -977,7 +977,7 @@ def VMLSD : ADbI<0b11100, 0b00, 1, 0,
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[(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">,
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Requires<[HasVFP2,UseFPVMLx,NoVFP4]>;
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Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
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def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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@ -985,7 +985,7 @@ def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
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[(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">,
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,NoVFP4]> {
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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@ -993,10 +993,10 @@ def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
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def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
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(VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
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Requires<[HasVFP2,UseFPVMLx,NoVFP4]>;
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Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
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def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
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(VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,NoVFP4]>;
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
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def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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@ -1004,7 +1004,7 @@ def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
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[(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">,
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Requires<[HasVFP2,UseFPVMLx,NoVFP4]>;
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Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
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def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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@ -1012,7 +1012,7 @@ def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
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[(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">,
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,NoVFP4]> {
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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@ -1020,10 +1020,10 @@ def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
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def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
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(VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
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Requires<[HasVFP2,UseFPVMLx,NoVFP4]>;
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Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
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def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
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(VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,NoVFP4]>;
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
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def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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@ -1031,14 +1031,14 @@ def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
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[(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">,
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Requires<[HasVFP2,UseFPVMLx,NoVFP4]>;
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Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
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def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
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[(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">,
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,NoVFP4]> {
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines on A8.
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let D = VFPNeonA8Domain;
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@ -1046,10 +1046,10 @@ def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
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def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
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(VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
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Requires<[HasVFP2,UseFPVMLx,NoVFP4]>;
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Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
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def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
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(VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,NoVFP4]>;
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Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
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//===----------------------------------------------------------------------===//
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// Fused FP Multiply-Accumulate Operations.
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@ -1060,7 +1060,7 @@ def VFMAD : ADbI<0b11101, 0b10, 0, 0,
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[(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">,
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Requires<[HasVFP4,FPContractions]>;
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Requires<[HasVFP4,UseFusedMAC]>;
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def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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@ -1068,17 +1068,17 @@ def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
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[(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">,
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Requires<[HasVFP4,DontUseNEONForFP,FPContractions]> {
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
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// Some single precision VFP instructions may be executed on both NEON and
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// VFP pipelines.
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}
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def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
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(VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
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Requires<[HasVFP4,FPContractions]>;
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Requires<[HasVFP4,UseFusedMAC]>;
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def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
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(VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
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Requires<[HasVFP4,DontUseNEONForFP,FPContractions]>;
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
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// Match @llvm.fma.* intrinsics
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def : Pat<(fma (f64 DPR:$Ddin), (f64 DPR:$Dn), (f64 DPR:$Dm)),
|
||||
@ -1094,7 +1094,7 @@ def VFMSD : ADbI<0b11101, 0b10, 1, 0,
|
||||
[(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
|
||||
(f64 DPR:$Ddin)))]>,
|
||||
RegConstraint<"$Ddin = $Dd">,
|
||||
Requires<[HasVFP4,FPContractions]>;
|
||||
Requires<[HasVFP4,UseFusedMAC]>;
|
||||
|
||||
def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
|
||||
(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
|
||||
@ -1102,17 +1102,17 @@ def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
|
||||
[(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
|
||||
SPR:$Sdin))]>,
|
||||
RegConstraint<"$Sdin = $Sd">,
|
||||
Requires<[HasVFP4,DontUseNEONForFP,FPContractions]> {
|
||||
Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
|
||||
// Some single precision VFP instructions may be executed on both NEON and
|
||||
// VFP pipelines.
|
||||
}
|
||||
|
||||
def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
|
||||
(VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
|
||||
Requires<[HasVFP4,FPContractions]>;
|
||||
Requires<[HasVFP4,UseFusedMAC]>;
|
||||
def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
|
||||
(VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
|
||||
Requires<[HasVFP4,DontUseNEONForFP,FPContractions]>;
|
||||
Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
|
||||
|
||||
def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
|
||||
(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
|
||||
@ -1120,7 +1120,7 @@ def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
|
||||
[(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
|
||||
(f64 DPR:$Ddin)))]>,
|
||||
RegConstraint<"$Ddin = $Dd">,
|
||||
Requires<[HasVFP4,FPContractions]>;
|
||||
Requires<[HasVFP4,UseFusedMAC]>;
|
||||
|
||||
def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
|
||||
(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
|
||||
@ -1128,17 +1128,17 @@ def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
|
||||
[(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
|
||||
SPR:$Sdin))]>,
|
||||
RegConstraint<"$Sdin = $Sd">,
|
||||
Requires<[HasVFP4,DontUseNEONForFP,FPContractions]> {
|
||||
Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
|
||||
// Some single precision VFP instructions may be executed on both NEON and
|
||||
// VFP pipelines.
|
||||
}
|
||||
|
||||
def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
|
||||
(VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
|
||||
Requires<[HasVFP4,FPContractions]>;
|
||||
Requires<[HasVFP4,UseFusedMAC]>;
|
||||
def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
|
||||
(VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
|
||||
Requires<[HasVFP4,DontUseNEONForFP,FPContractions]>;
|
||||
Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
|
||||
|
||||
// Match @llvm.fma.* intrinsics
|
||||
def : Pat<(fneg (fma (f64 DPR:$Ddin), (f64 DPR:$Dn), (f64 DPR:$Dm))),
|
||||
@ -1154,24 +1154,24 @@ def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
|
||||
[(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
|
||||
(f64 DPR:$Ddin)))]>,
|
||||
RegConstraint<"$Ddin = $Dd">,
|
||||
Requires<[HasVFP4,FPContractions]>;
|
||||
Requires<[HasVFP4,UseFusedMAC]>;
|
||||
|
||||
def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
|
||||
(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
|
||||
IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
|
||||
[(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
|
||||
RegConstraint<"$Sdin = $Sd">,
|
||||
Requires<[HasVFP4,DontUseNEONForFP,FPContractions]> {
|
||||
Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
|
||||
// Some single precision VFP instructions may be executed on both NEON and
|
||||
// VFP pipelines.
|
||||
}
|
||||
|
||||
def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
|
||||
(VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
|
||||
Requires<[HasVFP4,FPContractions]>;
|
||||
Requires<[HasVFP4,UseFusedMAC]>;
|
||||
def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
|
||||
(VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
|
||||
Requires<[HasVFP4,DontUseNEONForFP,FPContractions]>;
|
||||
Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP Conditional moves.
|
||||
|
@ -48,7 +48,6 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
|
||||
, HasVFPv3(false)
|
||||
, HasVFPv4(false)
|
||||
, HasNEON(false)
|
||||
, HasNEON2(false)
|
||||
, UseNEONForSinglePrecisionFP(false)
|
||||
, SlowFPVMLx(false)
|
||||
, HasVMLxForwarding(false)
|
||||
|
@ -45,13 +45,12 @@ protected:
|
||||
bool HasV6T2Ops;
|
||||
bool HasV7Ops;
|
||||
|
||||
/// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON, HasNEON2 - Specify what
|
||||
/// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON - Specify what
|
||||
/// floating point ISAs are supported.
|
||||
bool HasVFPv2;
|
||||
bool HasVFPv3;
|
||||
bool HasVFPv4;
|
||||
bool HasNEON;
|
||||
bool HasNEON2;
|
||||
|
||||
/// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
|
||||
/// specified. Use the method useNEONForSinglePrecisionFP() to
|
||||
@ -205,7 +204,6 @@ protected:
|
||||
bool hasVFP3() const { return HasVFPv3; }
|
||||
bool hasVFP4() const { return HasVFPv4; }
|
||||
bool hasNEON() const { return HasNEON; }
|
||||
bool hasNEON2() const { return HasNEON2 || (HasNEON && HasVFPv4); }
|
||||
bool useNEONForSinglePrecisionFP() const {
|
||||
return hasNEON() && UseNEONForSinglePrecisionFP; }
|
||||
|
||||
|
@ -1,7 +1,7 @@
|
||||
@ RUN: llvm-mc < %s -triple armv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=ARM
|
||||
@ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=THUMB
|
||||
|
||||
@ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee]
|
||||
@ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee]
|
||||
@ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b]
|
||||
vfma.f64 d16, d18, d17
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user