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FIX for PR1799: When a load is unfolded from an instruction, check if it is a new node. If not, do not create a new SUnit.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45157 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-12-18 08:42:10 +00:00
parent 88ce93e0ef
commit beec823d4b
2 changed files with 71 additions and 26 deletions
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62
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -429,21 +429,9 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, OldNumVals-1),
SDOperand(LoadNode, 1));
SUnit *LoadSU = NewSUnit(LoadNode);
SUnit *NewSU = NewSUnit(N);
SUnitMap[LoadNode].push_back(LoadSU);
SUnitMap[N].push_back(NewSU);
const TargetInstrDescriptor *TID = &TII->get(LoadNode->getTargetOpcode());
for (unsigned i = 0; i != TID->numOperands; ++i) {
if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) {
LoadSU->isTwoAddress = true;
break;
}
}
if (TID->Flags & M_COMMUTABLE)
LoadSU->isCommutable = true;
TID = &TII->get(N->getTargetOpcode());
const TargetInstrDescriptor *TID = &TII->get(N->getTargetOpcode());
for (unsigned i = 0; i != TID->numOperands; ++i) {
if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) {
NewSU->isTwoAddress = true;
@ -452,13 +440,30 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
}
if (TID->Flags & M_COMMUTABLE)
NewSU->isCommutable = true;
// FIXME: Calculate height / depth and propagate the changes?
LoadSU->Depth = NewSU->Depth = SU->Depth;
LoadSU->Height = NewSU->Height = SU->Height;
ComputeLatency(LoadSU);
NewSU->Depth = SU->Depth;
NewSU->Height = SU->Height;
ComputeLatency(NewSU);
// LoadNode may already exist. This can happen when there is another
// load from the same location and producing the same type of value
// but it has different alignment or volatileness.
bool isNewLoad = true;
SUnit *LoadSU;
DenseMap<SDNode*, std::vector<SUnit*> >::iterator SMI =
SUnitMap.find(LoadNode);
if (SMI != SUnitMap.end()) {
LoadSU = SMI->second.front();
isNewLoad = false;
} else {
LoadSU = NewSUnit(LoadNode);
SUnitMap[LoadNode].push_back(LoadSU);
LoadSU->Depth = SU->Depth;
LoadSU->Height = SU->Height;
ComputeLatency(LoadSU);
}
SUnit *ChainPred = NULL;
SmallVector<SDep, 4> ChainSuccs;
SmallVector<SDep, 4> LoadPreds;
@ -484,12 +489,14 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
}
SU->removePred(ChainPred, true, false);
LoadSU->addPred(ChainPred, true, false);
if (isNewLoad)
LoadSU->addPred(ChainPred, true, false);
for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
SDep *Pred = &LoadPreds[i];
SU->removePred(Pred->Dep, Pred->isCtrl, Pred->isSpecial);
LoadSU->addPred(Pred->Dep, Pred->isCtrl, Pred->isSpecial,
Pred->Reg, Pred->Cost);
if (isNewLoad)
LoadSU->addPred(Pred->Dep, Pred->isCtrl, Pred->isSpecial,
Pred->Reg, Pred->Cost);
}
for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
SDep *Pred = &NodePreds[i];
@ -506,12 +513,15 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
SDep *Succ = &ChainSuccs[i];
Succ->Dep->removePred(SU, Succ->isCtrl, Succ->isSpecial);
Succ->Dep->addPred(LoadSU, Succ->isCtrl, Succ->isSpecial,
Succ->Reg, Succ->Cost);
if (isNewLoad)
Succ->Dep->addPred(LoadSU, Succ->isCtrl, Succ->isSpecial,
Succ->Reg, Succ->Cost);
}
NewSU->addPred(LoadSU, false, false);
if (isNewLoad)
NewSU->addPred(LoadSU, false, false);
AvailableQueue->addNode(LoadSU);
if (isNewLoad)
AvailableQueue->addNode(LoadSU);
AvailableQueue->addNode(NewSU);
++NumUnfolds;
@ -519,8 +529,8 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
if (NewSU->NumSuccsLeft == 0) {
NewSU->isAvailable = true;
return NewSU;
} else
SU = NewSU;
}
SU = NewSU;
}
DOUT << "Duplicating SU # " << SU->NodeNum << "\n";

35
test/CodeGen/X86/2007-12-16-BURRSchedCrash.ll Normal file
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@ -0,0 +1,35 @@
; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu
; PR1799
%struct.c34007g__designated___XUB = type { i32, i32, i32, i32 }
%struct.c34007g__pkg__parent = type { i32*, %struct.c34007g__designated___XUB* }
define void @_ada_c34007g() {
entry:
%x8 = alloca %struct.c34007g__pkg__parent, align 8 ; <%struct.c34007g__pkg__parent*> [#uses=2]
br i1 true, label %bb1271, label %bb848
bb848: ; preds = %entry
ret void
bb1271: ; preds = %bb898
%tmp1272 = getelementptr %struct.c34007g__pkg__parent* %x8, i32 0, i32 0 ; <i32**> [#uses=1]
%x82167 = bitcast %struct.c34007g__pkg__parent* %x8 to i64* ; <i64*> [#uses=1]
br i1 true, label %bb4668, label %bb848
bb4668: ; preds = %bb4648
%tmp5464 = load i64* %x82167, align 8 ; <i64> [#uses=1]
%tmp5467 = icmp ne i64 0, %tmp5464 ; <i1> [#uses=1]
%tmp5470 = load i32** %tmp1272, align 8 ; <i32*> [#uses=1]
%tmp5471 = icmp eq i32* %tmp5470, null ; <i1> [#uses=1]
call fastcc void @c34007g__pkg__create.311( %struct.c34007g__pkg__parent* null, i32 7, i32 9, i32 2, i32 4, i32 1 )
%tmp5475 = or i1 %tmp5471, %tmp5467 ; <i1> [#uses=1]
%tmp5497 = or i1 %tmp5475, false ; <i1> [#uses=1]
br i1 %tmp5497, label %bb848, label %bb5507
bb5507: ; preds = %bb4668
ret void
}
declare fastcc void @c34007g__pkg__create.311(%struct.c34007g__pkg__parent*, i32, i32, i32, i32, i32)