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More extloads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75950 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -52,6 +52,9 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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setShiftAmountType(MVT::i32);
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// Provide all sorts of operation actions
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setStackPointerRegisterToSaveRestore(SystemZ::R15D);
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setSchedulingPreference(SchedulingForLatency);
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@ -176,14 +176,20 @@ def i64immZExt32 : PatLeaf<(i64 imm), [{
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}]>;
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// extloads
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def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
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def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
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def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
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def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
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def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
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def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
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def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
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def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
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def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
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def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
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def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
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def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
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def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
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def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
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def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
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@ -392,6 +398,12 @@ def MOV64mi16 : Pseudo<(outs), (ins riaddr:$dst, i64imm:$src),
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[(store (i64 immSExt16:$src), riaddr:$dst)]>;
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// extloads
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def MOVSX32rm8 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
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"lb\t{$dst, $src}",
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[(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
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def MOVSX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
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"lhy\t{$dst, $src}",
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[(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
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def MOVSX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lgb\t{$dst, $src}",
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[(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
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@ -402,6 +414,12 @@ def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lgf\t{$dst, $src}",
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[(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
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def MOVZX32rm8 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
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"llc\t{$dst, $src}",
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[(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
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def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
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"llh\t{$dst, $src}",
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[(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
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def MOVZX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"llgc\t{$dst, $src}",
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[(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
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@ -732,6 +750,8 @@ def : Pat<(sext_inreg GR64:$src, i32),
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(MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
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// extload patterns
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def : Pat<(extloadi32i8 rriaddr:$src), (MOVZX32rm8 rriaddr:$src)>;
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def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
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def : Pat<(extloadi64i8 rriaddr:$src), (MOVZX64rm8 rriaddr:$src)>;
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def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
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def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
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