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https://github.com/c64scene-ar/llvm-6502.git
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Remove some dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47036 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -910,8 +910,8 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
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}
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}
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static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
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static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
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unsigned *vRegs, unsigned ArgNo,
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unsigned ArgNo, unsigned &NumGPRs,
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unsigned &NumGPRs, unsigned &ArgOffset) {
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unsigned &ArgOffset) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFunction &MF = DAG.getMachineFunction();
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MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
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MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
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SDOperand Root = Op.getOperand(0);
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SDOperand Root = Op.getOperand(0);
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@ -936,19 +936,16 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
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if (ObjGPRs == 1) {
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if (ObjGPRs == 1) {
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unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
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unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
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RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
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RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
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vRegs[NumGPRs] = VReg;
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ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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if (ObjectVT == MVT::f32)
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if (ObjectVT == MVT::f32)
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ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
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ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
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} else if (ObjGPRs == 2) {
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} else if (ObjGPRs == 2) {
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unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
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unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
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RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
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RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
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vRegs[NumGPRs] = VReg;
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ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
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VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
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RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
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RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
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vRegs[NumGPRs+1] = VReg;
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SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
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assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
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@ -987,11 +984,10 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Root = Op.getOperand(0);
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SDOperand Root = Op.getOperand(0);
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unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
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unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
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unsigned NumGPRs = 0; // GPRs used for parameter passing.
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unsigned NumGPRs = 0; // GPRs used for parameter passing.
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unsigned VRegs[4];
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unsigned NumArgs = Op.Val->getNumValues()-1;
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unsigned NumArgs = Op.Val->getNumValues()-1;
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for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
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for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
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ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo,
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ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
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NumGPRs, ArgOffset));
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NumGPRs, ArgOffset));
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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