From bf2712ae4377e2e254ca0242c8b7b015bf4b26ec Mon Sep 17 00:00:00 2001 From: Kevin Enderby Date: Tue, 21 Jan 2014 00:18:51 +0000 Subject: [PATCH] To allow the X86 verbose assembly to print its informative comments when used with symbolic disassembly, add a check that the operand is an immediate and has not been symbolicated to MCExpr operand. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I’m trying to enable the ‘C’ disassembly API option LLVMDisassembler_Option_SetInstrComments for darwin’s otool(1) that uses the llvm disassembler API. The problem is that the disassembler API can change an immediate operand to an MCExpr operand if it symbolicates it with the call backs. And if it does the code in llvm::EmitAnyX86InstComments() will crash when it assumes these operands are immediates. The fix for this is very straight forward to just protect the call to getImm() with a check of isImm(). So if the immediate for an instruction is symbolicated it simply doesn’t get the X86 verbose assembly comments: % otool -tV test_asm.o test_asm.o: (__TEXT,__text) section _t1: 0000000000000000 vpshufd $_t1, %xmm1, %xmm0 0000000000000005 retq 0000000000000006 nopw %cs:_t1(%rax,%rax) _t2: 0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3] 0000000000000015 retq 0000000000000016 nopw %cs:_t1(%rax,%rax) _t3: 0000000000000020 vpshufd $_t1, %xmm1, %xmm0 0000000000000025 retq 0000000000000026 nopw %cs:_t1(%rax,%rax) _t4: 0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0] 0000000000000035 retq The fact that the immediate $0x0 is being symbolicated at all in this case is a different problem which my next patch will address. rdar://10989286 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../X86/InstPrinter/X86InstComments.cpp | 117 +++++++++++------- 1 file changed, 73 insertions(+), 44 deletions(-) diff --git a/lib/Target/X86/InstPrinter/X86InstComments.cpp b/lib/Target/X86/InstPrinter/X86InstComments.cpp index 0f6eeb19bcc..50ee968b5ba 100644 --- a/lib/Target/X86/InstPrinter/X86InstComments.cpp +++ b/lib/Target/X86/InstPrinter/X86InstComments.cpp @@ -38,7 +38,8 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, DestName = getRegName(MI->getOperand(0).getReg()); Src1Name = getRegName(MI->getOperand(1).getReg()); Src2Name = getRegName(MI->getOperand(2).getReg()); - DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); + if(MI->getOperand(3).isImm()) + DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); break; case X86::MOVLHPSrr: @@ -65,9 +66,10 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VPALIGNR128rm: Src2Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); - DecodePALIGNRMask(MVT::v16i8, - MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodePALIGNRMask(MVT::v16i8, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); break; case X86::VPALIGNR256rr: Src1Name = getRegName(MI->getOperand(2).getReg()); @@ -75,9 +77,10 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VPALIGNR256rm: Src2Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); - DecodePALIGNRMask(MVT::v32i8, - MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodePALIGNRMask(MVT::v32i8, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); break; case X86::PSHUFDri: @@ -87,16 +90,20 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::PSHUFDmi: case X86::VPSHUFDmi: DestName = getRegName(MI->getOperand(0).getReg()); - DecodePSHUFMask(MVT::v4i32, MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodePSHUFMask(MVT::v4i32, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); break; case X86::VPSHUFDYri: Src1Name = getRegName(MI->getOperand(1).getReg()); // FALL THROUGH. case X86::VPSHUFDYmi: DestName = getRegName(MI->getOperand(0).getReg()); - DecodePSHUFMask(MVT::v8i32, MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodePSHUFMask(MVT::v8i32, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); break; @@ -107,18 +114,20 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::PSHUFHWmi: case X86::VPSHUFHWmi: DestName = getRegName(MI->getOperand(0).getReg()); - DecodePSHUFHWMask(MVT::v8i16, - MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodePSHUFHWMask(MVT::v8i16, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); break; case X86::VPSHUFHWYri: Src1Name = getRegName(MI->getOperand(1).getReg()); // FALL THROUGH. case X86::VPSHUFHWYmi: DestName = getRegName(MI->getOperand(0).getReg()); - DecodePSHUFHWMask(MVT::v16i16, - MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodePSHUFHWMask(MVT::v16i16, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); break; case X86::PSHUFLWri: case X86::VPSHUFLWri: @@ -127,18 +136,20 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::PSHUFLWmi: case X86::VPSHUFLWmi: DestName = getRegName(MI->getOperand(0).getReg()); - DecodePSHUFLWMask(MVT::v8i16, - MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodePSHUFLWMask(MVT::v8i16, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); break; case X86::VPSHUFLWYri: Src1Name = getRegName(MI->getOperand(1).getReg()); // FALL THROUGH. case X86::VPSHUFLWYmi: DestName = getRegName(MI->getOperand(0).getReg()); - DecodePSHUFLWMask(MVT::v16i16, - MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodePSHUFLWMask(MVT::v16i16, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); break; case X86::PUNPCKHBWrr: @@ -293,8 +304,10 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, // FALL THROUGH. case X86::SHUFPDrmi: case X86::VSHUFPDrmi: - DecodeSHUFPMask(MVT::v2f64, MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodeSHUFPMask(MVT::v2f64, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -302,8 +315,10 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::VSHUFPDYrmi: - DecodeSHUFPMask(MVT::v4f64, MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodeSHUFPMask(MVT::v4f64, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -314,8 +329,10 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, // FALL THROUGH. case X86::SHUFPSrmi: case X86::VSHUFPSrmi: - DecodeSHUFPMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodeSHUFPMask(MVT::v4f32, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -323,8 +340,10 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::VSHUFPSYrmi: - DecodeSHUFPMask(MVT::v8f32, MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodeSHUFPMask(MVT::v8f32, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -405,32 +424,40 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, Src1Name = getRegName(MI->getOperand(1).getReg()); // FALL THROUGH. case X86::VPERMILPSmi: - DecodePSHUFMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodePSHUFMask(MVT::v4f32, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; case X86::VPERMILPSYri: Src1Name = getRegName(MI->getOperand(1).getReg()); // FALL THROUGH. case X86::VPERMILPSYmi: - DecodePSHUFMask(MVT::v8f32, MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodePSHUFMask(MVT::v8f32, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; case X86::VPERMILPDri: Src1Name = getRegName(MI->getOperand(1).getReg()); // FALL THROUGH. case X86::VPERMILPDmi: - DecodePSHUFMask(MVT::v2f64, MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodePSHUFMask(MVT::v2f64, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; case X86::VPERMILPDYri: Src1Name = getRegName(MI->getOperand(1).getReg()); // FALL THROUGH. case X86::VPERMILPDYmi: - DecodePSHUFMask(MVT::v4f64, MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodePSHUFMask(MVT::v4f64, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; case X86::VPERM2F128rr: @@ -440,9 +467,10 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VPERM2F128rm: case X86::VPERM2I128rm: // For instruction comments purpose, assume the 256-bit vector is v4i64. - DecodeVPERM2X128Mask(MVT::v4i64, - MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodeVPERM2X128Mask(MVT::v4i64, + MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -452,8 +480,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, // FALL THROUGH. case X86::VPERMQYmi: case X86::VPERMPDYmi: - DecodeVPERMMask(MI->getOperand(MI->getNumOperands()-1).getImm(), - ShuffleMask); + if(MI->getOperand(MI->getNumOperands()-1).isImm()) + DecodeVPERMMask(MI->getOperand(MI->getNumOperands()-1).getImm(), + ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; }