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ARM: produce friendly error for invalid inline asm

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We used to perform an invalid operation on an MVT and crash, which wasn't much
fun.

Patch by Oliver Stannard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194714 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2013-11-14 17:15:39 +00:00
parent 5e9f8c3948
commit bf7329d9a0
2 changed files with 20 additions and 0 deletions
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4
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -10860,6 +10860,8 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
case 'r':
return RCPair(0U, &ARM::GPRRegClass);
case 'w':
if (VT == MVT::Other)
break;
if (VT == MVT::f32)
return RCPair(0U, &ARM::SPRRegClass);
if (VT.getSizeInBits() == 64)
@ -10868,6 +10870,8 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
return RCPair(0U, &ARM::QPRRegClass);
break;
case 'x':
if (VT == MVT::Other)
break;
if (VT == MVT::f32)
return RCPair(0U, &ARM::SPR_8RegClass);
if (VT.getSizeInBits() == 64)

16
test/CodeGen/ARM/2013-11-08-inline-asm-neon-array.ll Normal file
View File

@ -0,0 +1,16 @@
;RUN: not llc -mtriple=arm-linux-gnueabihf < %s 2>&1 | FileCheck %s
; ModuleID = 'bug.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7--"
%struct.uint8x8x4_t = type { [4 x <8 x i8>] }
define void @foo() #0 {
%vsrc = alloca %struct.uint8x8x4_t, align 8
%ptr = alloca i8;
%1 = call i8* asm sideeffect "vld4.u8 ${0:h}, [$1], $2", "=*w,=r,r,1"(%struct.uint8x8x4_t* %vsrc, i32 0, i8* %ptr)
ret void
}
; CHECK: error: couldn't allocate output register for constraint 'w'