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AddressSanitizer instrumentation for MOV and MOVAPS.
This is an initial version of *Sanitizer instrumentation of assembly code. Patch by Yuri Gorshenin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203908 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evgeniy Stepanov
parent
1e83c8c3ab
commit
bf7cc396c6
@ -1,3 +1,4 @@
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add_llvm_library(LLVMX86AsmParser
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X86AsmInstrumentation.cpp
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X86AsmParser.cpp
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)
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236
lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
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236
lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
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@ -0,0 +1,236 @@
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//===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "X86AsmInstrumentation.h"
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#include "X86Operand.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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namespace llvm {
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namespace {
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static cl::opt<bool> ClAsanInstrumentInlineAssembly(
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"asan-instrument-inline-assembly", cl::desc("instrument inline assembly"),
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cl::Hidden, cl::init(false));
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bool IsStackReg(unsigned Reg) {
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return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
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}
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std::string FuncName(unsigned AccessSize, bool IsWrite) {
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return std::string("__sanitizer_sanitize_") + (IsWrite ? "store" : "load") +
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(utostr(AccessSize));
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}
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class X86AddressSanitizer : public X86AsmInstrumentation {
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public:
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X86AddressSanitizer(MCSubtargetInfo &sti) : STI(sti) {}
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virtual ~X86AddressSanitizer() {}
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// X86AsmInstrumentation implementation:
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virtual void InstrumentInstruction(
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const MCInst &Inst, SmallVectorImpl<MCParsedAsmOperand *> &Operands,
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MCContext &Ctx, MCStreamer &Out) override {
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InstrumentMOV(Inst, Operands, Ctx, Out);
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}
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// Should be implemented differently in x86_32 and x86_64 subclasses.
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virtual void InstrumentMemOperandImpl(X86Operand *Op, unsigned AccessSize,
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bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) = 0;
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void InstrumentMemOperand(MCParsedAsmOperand *Op, unsigned AccessSize,
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bool IsWrite, MCContext &Ctx, MCStreamer &Out);
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void InstrumentMOV(const MCInst &Inst,
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SmallVectorImpl<MCParsedAsmOperand *> &Operands,
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MCContext &Ctx, MCStreamer &Out);
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void EmitInstruction(MCStreamer &Out, const MCInst &Inst) {
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Out.EmitInstruction(Inst, STI);
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}
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protected:
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MCSubtargetInfo &STI;
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};
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void X86AddressSanitizer::InstrumentMemOperand(
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MCParsedAsmOperand *Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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assert(Op && Op->isMem() && "Op should be a memory operand.");
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assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
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"AccessSize should be a power of two, less or equal than 16.");
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X86Operand *MemOp = static_cast<X86Operand *>(Op);
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// FIXME: get rid of this limitation.
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if (IsStackReg(MemOp->getMemBaseReg()) || IsStackReg(MemOp->getMemIndexReg()))
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return;
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InstrumentMemOperandImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
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}
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void X86AddressSanitizer::InstrumentMOV(
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const MCInst &Inst, SmallVectorImpl<MCParsedAsmOperand *> &Operands,
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MCContext &Ctx, MCStreamer &Out) {
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// Access size in bytes.
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unsigned AccessSize = 0;
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unsigned long OpIx = Operands.size();
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switch (Inst.getOpcode()) {
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case X86::MOV8mi:
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case X86::MOV8mr:
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AccessSize = 1;
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OpIx = 2;
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break;
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case X86::MOV8rm:
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AccessSize = 1;
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OpIx = 1;
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break;
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case X86::MOV16mi:
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case X86::MOV16mr:
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AccessSize = 2;
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OpIx = 2;
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break;
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case X86::MOV16rm:
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AccessSize = 2;
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OpIx = 1;
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break;
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case X86::MOV32mi:
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case X86::MOV32mr:
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AccessSize = 4;
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OpIx = 2;
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break;
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case X86::MOV32rm:
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AccessSize = 4;
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OpIx = 1;
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break;
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case X86::MOV64mi32:
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case X86::MOV64mr:
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AccessSize = 8;
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OpIx = 2;
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break;
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case X86::MOV64rm:
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AccessSize = 8;
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OpIx = 1;
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break;
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case X86::MOVAPDmr:
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case X86::MOVAPSmr:
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AccessSize = 16;
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OpIx = 2;
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break;
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case X86::MOVAPDrm:
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case X86::MOVAPSrm:
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AccessSize = 16;
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OpIx = 1;
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break;
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}
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if (OpIx >= Operands.size())
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return;
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const bool IsWrite = (OpIx != 1);
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InstrumentMemOperand(Operands[OpIx], AccessSize, IsWrite, Ctx, Out);
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}
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class X86AddressSanitizer32 : public X86AddressSanitizer {
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public:
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X86AddressSanitizer32(MCSubtargetInfo &sti) : X86AddressSanitizer(sti) {}
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virtual ~X86AddressSanitizer32() {}
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virtual void InstrumentMemOperandImpl(X86Operand *Op, unsigned AccessSize,
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bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) override;
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};
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void X86AddressSanitizer32::InstrumentMemOperandImpl(
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X86Operand *Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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// FIXME: emit .cfi directives for correct stack unwinding.
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
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{
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(X86::EAX));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
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{
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const std::string Func = FuncName(AccessSize, IsWrite);
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const MCSymbol *FuncSym = Ctx.GetOrCreateSymbol(StringRef(Func));
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const MCSymbolRefExpr *FuncExpr =
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MCSymbolRefExpr::Create(FuncSym, MCSymbolRefExpr::VK_PLT, Ctx);
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EmitInstruction(Out, MCInstBuilder(X86::CALLpcrel32).addExpr(FuncExpr));
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}
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EmitInstruction(Out, MCInstBuilder(X86::ADD32ri).addReg(X86::ESP)
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.addReg(X86::ESP).addImm(4));
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EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
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}
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class X86AddressSanitizer64 : public X86AddressSanitizer {
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public:
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X86AddressSanitizer64(MCSubtargetInfo &sti) : X86AddressSanitizer(sti) {}
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virtual ~X86AddressSanitizer64() {}
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virtual void InstrumentMemOperandImpl(X86Operand *Op, unsigned AccessSize,
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bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) override;
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};
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void X86AddressSanitizer64::InstrumentMemOperandImpl(
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X86Operand *Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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// FIXME: emit .cfi directives for correct stack unwinding.
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// Set %rsp below current red zone (128 bytes wide)
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EmitInstruction(Out, MCInstBuilder(X86::SUB64ri32).addReg(X86::RSP)
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.addReg(X86::RSP).addImm(128));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RDI));
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{
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MCInst Inst;
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Inst.setOpcode(X86::LEA64r);
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Inst.addOperand(MCOperand::CreateReg(X86::RDI));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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{
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const std::string Func = FuncName(AccessSize, IsWrite);
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const MCSymbol *FuncSym = Ctx.GetOrCreateSymbol(StringRef(Func));
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const MCSymbolRefExpr *FuncExpr =
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MCSymbolRefExpr::Create(FuncSym, MCSymbolRefExpr::VK_PLT, Ctx);
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EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FuncExpr));
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}
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EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RDI));
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EmitInstruction(Out, MCInstBuilder(X86::ADD64ri32).addReg(X86::RSP)
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.addReg(X86::RSP).addImm(128));
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}
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} // End anonymous namespace
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X86AsmInstrumentation::X86AsmInstrumentation() {}
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X86AsmInstrumentation::~X86AsmInstrumentation() {}
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void X86AsmInstrumentation::InstrumentInstruction(
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const MCInst &Inst, SmallVectorImpl<MCParsedAsmOperand *> &Operands,
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MCContext &Ctx, MCStreamer &Out) {}
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X86AsmInstrumentation *CreateX86AsmInstrumentation(MCSubtargetInfo &STI) {
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if (ClAsanInstrumentInlineAssembly) {
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if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
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return new X86AddressSanitizer32(STI);
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if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
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return new X86AddressSanitizer64(STI);
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}
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return new X86AsmInstrumentation();
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}
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} // End llvm namespace
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46
lib/Target/X86/AsmParser/X86AsmInstrumentation.h
Normal file
46
lib/Target/X86/AsmParser/X86AsmInstrumentation.h
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@ -0,0 +1,46 @@
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//===- X86AsmInstrumentation.h - Instrument X86 inline assembly *- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86_ASM_INSTRUMENTATION_H
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#define X86_ASM_INSTRUMENTATION_H
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#include "llvm/ADT/SmallVector.h"
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namespace llvm {
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class MCContext;
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class MCInst;
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class MCParsedAsmOperand;
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class MCStreamer;
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class MCSubtargetInfo;
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class X86AsmInstrumentation;
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X86AsmInstrumentation *CreateX86AsmInstrumentation(MCSubtargetInfo &STI);
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class X86AsmInstrumentation {
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public:
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virtual ~X86AsmInstrumentation();
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// Instruments Inst. Should be called just before the original
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// instruction is sent to Out.
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virtual void InstrumentInstruction(
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const MCInst &Inst, SmallVectorImpl<MCParsedAsmOperand *> &Operands,
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MCContext &Ctx, MCStreamer &Out);
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protected:
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friend X86AsmInstrumentation *
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CreateX86AsmInstrumentation(MCSubtargetInfo &STI);
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X86AsmInstrumentation();
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};
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} // End llvm namespace
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#endif // X86_ASM_INSTRUMENTATION_H
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@ -8,6 +8,7 @@
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "X86AsmInstrumentation.h"
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#include "X86AsmParserCommon.h"
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#include "X86Operand.h"
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#include "llvm/ADT/APFloat.h"
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@ -30,6 +31,7 @@
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include <memory>
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using namespace llvm;
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@ -54,6 +56,7 @@ class X86AsmParser : public MCTargetAsmParser {
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MCSubtargetInfo &STI;
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MCAsmParser &Parser;
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ParseInstructionInfo *InstInfo;
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std::unique_ptr<X86AsmInstrumentation> Instrumentation;
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private:
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SMLoc consumeToken() {
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SMLoc Result = Parser.getTok().getLoc();
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@ -650,6 +653,12 @@ private:
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bool processInstruction(MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
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/// Wrapper around MCStreamer::EmitInstruction(). Possibly adds
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/// instrumentation around Inst.
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void EmitInstruction(MCInst &Inst,
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SmallVectorImpl<MCParsedAsmOperand *> &Operands,
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MCStreamer &Out);
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out, unsigned &ErrorInfo,
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@ -706,6 +715,7 @@ public:
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// Initialize the set of available features.
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setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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Instrumentation.reset(CreateX86AsmInstrumentation(STI));
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}
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bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
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@ -2239,6 +2249,14 @@ processInstruction(MCInst &Inst,
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}
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static const char *getSubtargetFeatureName(unsigned Val);
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void X86AsmParser::EmitInstruction(
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MCInst &Inst, SmallVectorImpl<MCParsedAsmOperand *> &Operands,
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MCStreamer &Out) {
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Instrumentation->InstrumentInstruction(Inst, Operands, getContext(), Out);
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Out.EmitInstruction(Inst, STI);
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}
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bool X86AsmParser::
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MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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@ -2261,7 +2279,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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Inst.setOpcode(X86::WAIT);
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Inst.setLoc(IDLoc);
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if (!MatchingInlineAsm)
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Out.EmitInstruction(Inst, STI);
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EmitInstruction(Inst, Operands, Out);
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const char *Repl =
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StringSwitch<const char*>(Op->getToken())
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@ -2297,7 +2315,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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Inst.setLoc(IDLoc);
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if (!MatchingInlineAsm)
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Out.EmitInstruction(Inst, STI);
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EmitInstruction(Inst, Operands, Out);
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Opcode = Inst.getOpcode();
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return false;
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case Match_MissingFeature: {
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@ -2384,7 +2402,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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if (NumSuccessfulMatches == 1) {
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Inst.setLoc(IDLoc);
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if (!MatchingInlineAsm)
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Out.EmitInstruction(Inst, STI);
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EmitInstruction(Inst, Operands, Out);
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Opcode = Inst.getOpcode();
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return false;
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}
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123
test/Instrumentation/AddressSanitizer/X86/asm_mov.ll
Normal file
123
test/Instrumentation/AddressSanitizer/X86/asm_mov.ll
Normal file
@ -0,0 +1,123 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+sse2 -asan-instrument-inline-assembly | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; CHECK-LABEL: mov1b
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; CHECK: subq $128, %rsp
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; CHECK-NEXT: pushq %rdi
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; CHECK-NEXT: leaq {{.*}}, %rdi
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; CHECK-NEXT: callq __sanitizer_sanitize_load1@PLT
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; CHECK-NEXT: popq %rdi
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; CHECK-NEXT: addq $128, %rsp
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; CHECK: subq $128, %rsp
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; CHECK-NEXT: pushq %rdi
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; CHECK-NEXT: leaq {{.*}}, %rdi
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; CHECK-NEXT: callq __sanitizer_sanitize_store1@PLT
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; CHECK-NEXT: popq %rdi
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; CHECK-NEXT: addq $128, %rsp
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; CHECK: movb {{.*}}, {{.*}}
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define void @mov1b(i8* %dst, i8* %src) #0 {
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entry:
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tail call void asm sideeffect "movb ($1), %al \0A\09movb %al, ($0) \0A\09", "r,r,~{memory},~{rax},~{dirflag},~{fpsr},~{flags}"(i8* %dst, i8* %src) #1, !srcloc !0
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ret void
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}
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; CHECK-LABEL: mov2b
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; CHECK: subq $128, %rsp
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; CHECK-NEXT: pushq %rdi
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; CHECK-NEXT: leaq {{.*}}, %rdi
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; CHECK-NEXT: callq __sanitizer_sanitize_load2@PLT
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; CHECK-NEXT: popq %rdi
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; CHECK-NEXT: addq $128, %rsp
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; CHECK: subq $128, %rsp
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; CHECK-NEXT: pushq %rdi
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; CHECK-NEXT: leaq {{.*}}, %rdi
|
||||
; CHECK-NEXT: callq __sanitizer_sanitize_store2@PLT
|
||||
; CHECK-NEXT: popq %rdi
|
||||
; CHECK-NEXT: addq $128, %rsp
|
||||
|
||||
; CHECK: movw {{.*}}, {{.*}}
|
||||
define void @mov2b(i16* %dst, i16* %src) #0 {
|
||||
entry:
|
||||
tail call void asm sideeffect "movw ($1), %ax \0A\09movw %ax, ($0) \0A\09", "r,r,~{memory},~{rax},~{dirflag},~{fpsr},~{flags}"(i16* %dst, i16* %src) #1, !srcloc !1
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: mov4b
|
||||
; CHECK: subq $128, %rsp
|
||||
; CHECK-NEXT: pushq %rdi
|
||||
; CHECK-NEXT: leaq {{.*}}, %rdi
|
||||
; CHECK-NEXT: callq __sanitizer_sanitize_load4@PLT
|
||||
; CHECK-NEXT: popq %rdi
|
||||
; CHECK-NEXT: addq $128, %rsp
|
||||
|
||||
; CHECK: subq $128, %rsp
|
||||
; CHECK-NEXT: pushq %rdi
|
||||
; CHECK-NEXT: leaq {{.*}}, %rdi
|
||||
; CHECK-NEXT: callq __sanitizer_sanitize_store4@PLT
|
||||
; CHECK-NEXT: popq %rdi
|
||||
; CHECK-NEXT: addq $128, %rsp
|
||||
|
||||
; CHECK: movl {{.*}}, {{.*}}
|
||||
define void @mov4b(i32* %dst, i32* %src) #0 {
|
||||
entry:
|
||||
tail call void asm sideeffect "movl ($1), %eax \0A\09movl %eax, ($0) \0A\09", "r,r,~{memory},~{rax},~{dirflag},~{fpsr},~{flags}"(i32* %dst, i32* %src) #1, !srcloc !2
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: mov8b
|
||||
; CHECK: subq $128, %rsp
|
||||
; CHECK-NEXT: pushq %rdi
|
||||
; CHECK-NEXT: leaq {{.*}}, %rdi
|
||||
; CHECK-NEXT: callq __sanitizer_sanitize_load8@PLT
|
||||
; CHECK-NEXT: popq %rdi
|
||||
; CHECK-NEXT: addq $128, %rsp
|
||||
|
||||
; CHECK: subq $128, %rsp
|
||||
; CHECK-NEXT: pushq %rdi
|
||||
; CHECK-NEXT: leaq {{.*}}, %rdi
|
||||
; CHECK-NEXT: callq __sanitizer_sanitize_store8@PLT
|
||||
; CHECK-NEXT: popq %rdi
|
||||
; CHECK-NEXT: addq $128, %rsp
|
||||
|
||||
; CHECK: movq {{.*}}, {{.*}}
|
||||
define void @mov8b(i64* %dst, i64* %src) #0 {
|
||||
entry:
|
||||
tail call void asm sideeffect "movq ($1), %rax \0A\09movq %rax, ($0) \0A\09", "r,r,~{memory},~{rax},~{dirflag},~{fpsr},~{flags}"(i64* %dst, i64* %src) #1, !srcloc !3
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: mov16b
|
||||
; CHECK: subq $128, %rsp
|
||||
; CHECK-NEXT: pushq %rdi
|
||||
; CHECK-NEXT: leaq {{.*}}, %rdi
|
||||
; CHECK-NEXT: callq __sanitizer_sanitize_load16@PLT
|
||||
; CHECK-NEXT: popq %rdi
|
||||
; CHECK-NEXT: addq $128, %rsp
|
||||
|
||||
; CHECK: subq $128, %rsp
|
||||
; CHECK-NEXT: pushq %rdi
|
||||
; CHECK-NEXT: leaq {{.*}}, %rdi
|
||||
; CHECK-NEXT: callq __sanitizer_sanitize_store16@PLT
|
||||
; CHECK-NEXT: popq %rdi
|
||||
; CHECK-NEXT: addq $128, %rsp
|
||||
|
||||
; CHECK: movaps {{.*}}, {{.*}}
|
||||
define void @mov16b(<2 x i64>* %dst, <2 x i64>* %src) #0 {
|
||||
entry:
|
||||
tail call void asm sideeffect "movaps ($1), %xmm0 \0A\09movaps %xmm0, ($0) \0A\09", "r,r,~{memory},~{xmm0},~{dirflag},~{fpsr},~{flags}"(<2 x i64>* %dst, <2 x i64>* %src) #1, !srcloc !4
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { nounwind }
|
||||
|
||||
!0 = metadata !{i32 98, i32 122, i32 160}
|
||||
!1 = metadata !{i32 305, i32 329, i32 367}
|
||||
!2 = metadata !{i32 512, i32 537, i32 576}
|
||||
!3 = metadata !{i32 721, i32 746, i32 785}
|
||||
!4 = metadata !{i32 929, i32 957, i32 999}
|
||||
76
test/Instrumentation/AddressSanitizer/X86/asm_mov.s
Normal file
76
test/Instrumentation/AddressSanitizer/X86/asm_mov.s
Normal file
@ -0,0 +1,76 @@
|
||||
# RUN: llvm-mc %s -triple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+sse2 -asan-instrument-inline-assembly | FileCheck %s
|
||||
|
||||
.text
|
||||
.globl mov1b
|
||||
.align 16, 0x90
|
||||
.type mov1b,@function
|
||||
# CHECK-LABEL: mov1b:
|
||||
#
|
||||
# CHECK: subq $128, %rsp
|
||||
# CHECK-NEXT: pushq %rdi
|
||||
# CHECK-NEXT: leaq (%rsi), %rdi
|
||||
# CHECK-NEXT: callq __sanitizer_sanitize_load1@PLT
|
||||
# CHECK-NEXT: popq %rdi
|
||||
# CHECK-NEXT: addq $128, %rsp
|
||||
#
|
||||
# CHECK-NEXT: movb (%rsi), %al
|
||||
#
|
||||
# CHECK-NEXT: subq $128, %rsp
|
||||
# CHECK-NEXT: pushq %rdi
|
||||
# CHECK-NEXT: leaq (%rdi), %rdi
|
||||
# CHECK-NEXT: callq __sanitizer_sanitize_store1@PLT
|
||||
# CHECK-NEXT: popq %rdi
|
||||
# CHECK-NEXT: addq $128, %rsp
|
||||
#
|
||||
# CHECK-NEXT: movb %al, (%rdi)
|
||||
mov1b: # @mov1b
|
||||
.cfi_startproc
|
||||
# BB#0:
|
||||
#APP
|
||||
movb (%rsi), %al
|
||||
movb %al, (%rdi)
|
||||
|
||||
#NO_APP
|
||||
retq
|
||||
.Ltmp0:
|
||||
.size mov1b, .Ltmp0-mov1b
|
||||
.cfi_endproc
|
||||
|
||||
.globl mov16b
|
||||
.align 16, 0x90
|
||||
.type mov16b,@function
|
||||
# CHECK-LABEL: mov16b:
|
||||
#
|
||||
# CHECK: subq $128, %rsp
|
||||
# CHECK-NEXT: pushq %rdi
|
||||
# CHECK-NEXT: leaq (%rsi), %rdi
|
||||
# CHECK-NEXT: callq __sanitizer_sanitize_load16@PLT
|
||||
# CHECK-NEXT: popq %rdi
|
||||
# CHECK-NEXT: addq $128, %rsp
|
||||
#
|
||||
# CHECK-NEXT: movaps (%rsi), %xmm0
|
||||
#
|
||||
# CHECK-NEXT: subq $128, %rsp
|
||||
# CHECK-NEXT: pushq %rdi
|
||||
# CHECK-NEXT: leaq (%rdi), %rdi
|
||||
# CHECK-NEXT: callq __sanitizer_sanitize_store16@PLT
|
||||
# CHECK-NEXT: popq %rdi
|
||||
# CHECK-NEXT: addq $128, %rsp
|
||||
#
|
||||
# CHECK-NEXT: movaps %xmm0, (%rdi)
|
||||
mov16b: # @mov16b
|
||||
.cfi_startproc
|
||||
# BB#0:
|
||||
#APP
|
||||
movaps (%rsi), %xmm0
|
||||
movaps %xmm0, (%rdi)
|
||||
|
||||
#NO_APP
|
||||
retq
|
||||
.Ltmp1:
|
||||
.size mov16b, .Ltmp1-mov16b
|
||||
.cfi_endproc
|
||||
|
||||
|
||||
.ident "clang version 3.5 "
|
||||
.section ".note.GNU-stack","",@progbits
|
||||
@ -0,0 +1,44 @@
|
||||
# RUN: llvm-mc %s -triple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+sse2 | FileCheck %s
|
||||
|
||||
.text
|
||||
.globl mov1b
|
||||
.align 16, 0x90
|
||||
.type mov1b,@function
|
||||
# CHECK-LABEL: mov1b
|
||||
# CHECK-NOT: callq __sanitizer_sanitize_load1@PLT
|
||||
# CHECK-NOT: callq __sanitizer_sanitize_store1@PLT
|
||||
mov1b: # @mov1b
|
||||
.cfi_startproc
|
||||
# BB#0:
|
||||
#APP
|
||||
movb (%rsi), %al
|
||||
movb %al, (%rdi)
|
||||
|
||||
#NO_APP
|
||||
retq
|
||||
.Ltmp0:
|
||||
.size mov1b, .Ltmp0-mov1b
|
||||
.cfi_endproc
|
||||
|
||||
.globl mov16b
|
||||
.align 16, 0x90
|
||||
.type mov16b,@function
|
||||
# CHECK-LABEL: mov16b
|
||||
# CHECK-NOT: callq __sanitizer_sanitize_load16@PLT
|
||||
# CHECK-NOT: callq __sanitizer_sanitize_store16@PLT
|
||||
mov16b: # @mov16b
|
||||
.cfi_startproc
|
||||
# BB#0:
|
||||
#APP
|
||||
movaps (%rsi), %xmm0
|
||||
movaps %xmm0, (%rdi)
|
||||
|
||||
#NO_APP
|
||||
retq
|
||||
.Ltmp1:
|
||||
.size mov16b, .Ltmp1-mov16b
|
||||
.cfi_endproc
|
||||
|
||||
|
||||
.ident "clang version 3.5 "
|
||||
.section ".note.GNU-stack","",@progbits
|
||||
Loading…
x
Reference in New Issue
Block a user