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Change register allocation order to Dale's suggestion.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35021 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-03-08 02:56:40 +00:00
parent 11788fde93
commit bf822eb6a3
1 changed files with 18 additions and 14 deletions
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32
lib/Target/ARM/ARMRegisterInfo.td
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@ -99,30 +99,34 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
// generate large stack offset. Make it available once we have register
// scavenging. Similarly r3 is reserved in Thumb mode for now.
let MethodBodies = [{
// FP is R11, R9 is available, R12 is available.
// FP is R11, R9 is available.
static const unsigned ARM_GPR_AO_1[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0,
ARM::R12,ARM::LR,
ARM::R4, ARM::R5, ARM::R6, ARM::R7,
ARM::R8, ARM::R9, ARM::R10,ARM::R12,
ARM::LR, ARM::R11 };
// FP is R11, R9 is not available, R12 is available.
ARM::R8, ARM::R9, ARM::R10,
ARM::R11 };
// FP is R11, R9 is not available.
static const unsigned ARM_GPR_AO_2[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0,
ARM::R12,ARM::LR,
ARM::R4, ARM::R5, ARM::R6, ARM::R7,
ARM::R8, ARM::R10,ARM::R12,
ARM::LR, ARM::R11 };
// FP is R7, R9 is available, R12 is available.
ARM::R8, ARM::R10,
ARM::R11 };
// FP is R7, R9 is available.
static const unsigned ARM_GPR_AO_3[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0,
ARM::R4, ARM::R5, ARM::R6, ARM::R8,
ARM::R9, ARM::R10,ARM::R11,ARM::R12,
ARM::LR, ARM::R7 };
// FP is R7, R9 is not available, R12 is available.
ARM::R12,ARM::LR,
ARM::R4, ARM::R5, ARM::R6,
ARM::R8, ARM::R9, ARM::R10,ARM::R11,
ARM::R7 };
// FP is R7, R9 is not available.
static const unsigned ARM_GPR_AO_4[] = {
ARM::R3, ARM::R2, ARM::R1, ARM::R0,
ARM::R4, ARM::R5, ARM::R6, ARM::R8,
ARM::R10,ARM::R11,ARM::R12,
ARM::LR, ARM::R7 };
ARM::R12,ARM::LR,
ARM::R4, ARM::R5, ARM::R6,
ARM::R8, ARM::R10,ARM::R11,
ARM::R7 };
// FP is R7, only low registers available.
static const unsigned THUMB_GPR_AO[] = {