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Add 8bit shifts

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70759 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-05-03 13:16:37 +00:00
parent e699d0f549
commit bf8ef3f29d
4 changed files with 28 additions and 15 deletions
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9
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
View File

@ -127,8 +127,15 @@ bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue Addr,
void MSP430DAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump());
// Select target instructions for the DAG.
// Codegen the basic block.
#ifndef NDEBUG
DOUT << "===== Instruction selection begins:\n";
Indent = 0;
#endif
SelectRoot(*CurDAG);
#ifndef NDEBUG
DOUT << "===== Instruction selection ends:\n";
#endif
CurDAG->RemoveDeadNodes();
}

7
lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -67,6 +67,9 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
// We don't have any truncstores
setTruncStoreAction(MVT::i16, MVT::i8, Expand);
setOperationAction(ISD::SRA, MVT::i8, Custom);
setOperationAction(ISD::SHL, MVT::i8, Custom);
setOperationAction(ISD::SRL, MVT::i8, Custom);
setOperationAction(ISD::SRA, MVT::i16, Custom);
setOperationAction(ISD::SHL, MVT::i16, Custom);
setOperationAction(ISD::SRL, MVT::i16, Custom);
@ -450,8 +453,7 @@ SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
if (Opc == ISD::SRL && ShiftAmount) {
// Emit a special goodness here:
// srl A, 1 => clrc; rrc A
SDValue clrc = DAG.getNode(MSP430ISD::CLRC, dl, MVT::Other);
Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim, clrc);
Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
ShiftAmount -= 1;
}
@ -603,7 +605,6 @@ const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
case MSP430ISD::CMP: return "MSP430ISD::CMP";
case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
case MSP430ISD::SELECT: return "MSP430ISD::SELECT";
case MSP430ISD::CLRC: return "MSP430ISD::CLRC";
}
}

5
lib/Target/MSP430/MSP430ISelLowering.h
View File

@ -56,10 +56,7 @@ namespace llvm {
/// SELECT. Operand 0 and operand 1 are selection variable, operand 3 is
/// condition code and operand 4 is flag operand.
SELECT,
/// CLRC - Clear carry bit
CLRC
SELECT
};
}

22
lib/Target/MSP430/MSP430InstrInfo.td
View File

@ -33,7 +33,6 @@ def SDT_MSP430BrCond : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>,
SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
def SDT_MSP430Select : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
SDTCisVT<3, i8>, SDTCisVT<4, i16>]>;
def SDT_MSP430Clrc : SDTypeProfile<0, 0, []>;
//===----------------------------------------------------------------------===//
// MSP430 Specific Node Definitions.
@ -43,7 +42,7 @@ def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
def MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>;
def MSP430rrc : SDNode<"MSP430ISD::RRC", SDTIntUnaryOp, [SDNPInFlag]>;
def MSP430rrc : SDNode<"MSP430ISD::RRC", SDTIntUnaryOp, []>;
def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
@ -58,7 +57,6 @@ def MSP430setcc : SDNode<"MSP430ISD::SETCC", SDT_MSP430SetCC>;
def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp>;
def MSP430brcond : SDNode<"MSP430ISD::BRCOND", SDT_MSP430BrCond, [SDNPHasChain]>;
def MSP430select : SDNode<"MSP430ISD::SELECT", SDT_MSP430Select>;
def MSP430clrc : SDNode<"MSP430ISD::CLRC", SDT_MSP430Clrc, [SDNPOutFlag]>;
//===----------------------------------------------------------------------===//
// MSP430 Operand Definitions.
@ -590,17 +588,31 @@ def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
} // Uses = [SRW]
// FIXME: Provide proper encoding!
def SAR8r1 : Pseudo<(outs GR8:$dst), (ins GR8:$src),
"rra.b\t$dst",
[(set GR8:$dst, (MSP430rra GR8:$src)),
(implicit SRW)]>;
def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
"rra.w\t$dst",
[(set GR16:$dst, (MSP430rra GR16:$src)),
(implicit SRW)]>;
def SHL8r1 : Pseudo<(outs GR8:$dst), (ins GR8:$src),
"rla.b\t$dst",
[(set GR8:$dst, (MSP430rla GR8:$src)),
(implicit SRW)]>;
def SHL16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
"rla.w\t$dst",
[(set GR16:$dst, (MSP430rla GR16:$src)),
(implicit SRW)]>;
def SAR8r1c : Pseudo<(outs GR8:$dst), (ins GR8:$src),
"clrc\n"
"rrc.b\t$dst",
[(set GR8:$dst, (MSP430rrc GR8:$src)),
(implicit SRW)]>;
def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src),
"clrc\n"
"rrc.w\t$dst",
[(set GR16:$dst, (MSP430rrc GR16:$src)),
(implicit SRW)]>;
@ -670,10 +682,6 @@ def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
} // isTwoAddress = 1
let Defs = [SRW] in
def CLRC : Pseudo<(outs), (ins),
"clrc", [(MSP430clrc)]>;
// Integer comparisons
let Defs = [SRW] in {
def CMP8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2),