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Change this code ot pass register classes into the stack slot spiller/reloader

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code.  PrologEpilogInserter hasn't been updated yet though, so targets cannot
use this info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23536 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-09-30 01:29:00 +00:00
parent 294f41d5fc
commit bf9716b9c4
4 changed files with 19 additions and 11 deletions
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lib/CodeGen/RegAllocLocal.cpp
+2 -2
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@@ -270,7 +270,7 @@ void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC);
DEBUG(std::cerr << " to stack slot #" << FrameIndex);
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex);
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
++NumStores; // Update statistics
}
@@ -476,7 +476,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
<< RegInfo->getName(PhysReg) << "\n");
// Add move instruction(s)
RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex);
RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads; // Update statistics
PhysRegsEverUsed[PhysReg] = true;