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Fix instruction scheduling live register tracking

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Summary:
This patch fixes PR23405 (https://llvm.org/bugs/show_bug.cgi?id=23405).

During a node unscheduling an entry in LiveRegGens can be replaced with a new value. That corrupts the live reg tracking and LiveReg* structure is not cleared as should be during unscheduling. Problematic condition that enforces Gen replacement is `I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight()`. This condition should be checked only if LiveRegGen was set in current node unscheduling.

Test Plan: Regression test included.

Reviewers: hfinkel, atrick

Reviewed By: atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9993

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240538 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Pawel Bylica 2015-06-24 12:49:42 +00:00
parent 611e493ece
commit bf98467060
2 changed files with 43 additions and 8 deletions
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25
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -848,17 +848,26 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
}
}
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
I != E; ++I) {
if (I->isAssignedRegDep()) {
if (!LiveRegDefs[I->getReg()])
for (auto &Succ : SU->Succs) {
if (Succ.isAssignedRegDep()) {
auto Reg = Succ.getReg();
if (!LiveRegDefs[Reg])
++NumLiveRegs;
// This becomes the nearest def. Note that an earlier def may still be
// pending if this is a two-address node.
LiveRegDefs[I->getReg()] = SU;
if (LiveRegGens[I->getReg()] == nullptr ||
I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight())
LiveRegGens[I->getReg()] = I->getSUnit();
LiveRegDefs[Reg] = SU;
// Update LiveRegGen only if was empty before this unscheduling.
// This is to avoid incorrect updating LiveRegGen set in previous run.
if (!LiveRegGens[Reg]) {
// Find the successor with the lowest height.
LiveRegGens[Reg] = Succ.getSUnit();
for (auto &Succ2 : SU->Succs) {
if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg &&
Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight())
LiveRegGens[Reg] = Succ2.getSUnit();
}
}
}
}
if (SU->getHeight() < MinAvailableCycle)

26
test/CodeGen/X86/rrlist-livereg-corrutpion.ll Normal file
View File

@ -0,0 +1,26 @@
; RUN: llc < %s -march=x86-64 | FileCheck %s
; CHECK-LABEL: test
define i64 @test(i64 %a, i256 %b, i1 %c) {
%u = zext i64 %a to i256
%s = add i256 %u, 1
%o = trunc i256 %s to i1
%j = add i256 %s, 1
%i = icmp ule i64 %a, 1
%f = select i1 %o, i256 undef, i256 %j
%d = select i1 %i, i256 %f, i256 1
%e = add i256 %b, 1
%n = select i1 %c, i256 %e, i256 %b
%m = trunc i256 %n to i64
%h = add i64 %m, 1
%r = zext i64 %h to i256
%v = lshr i256 %d, %r
%t = trunc i256 %v to i1
%q = shl i256 1, %r
%p = and i256 %d, %q
%w = icmp ule i256 %n, 1
%y = select i1 %t, i256 undef, i256 %p
%x = select i1 %w, i256 %y, i256 %d
%z = trunc i256 %x to i64
ret i64 %z
}