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[SystemZ] Add LOCR and LOCGR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187113 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -680,6 +680,36 @@ class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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let OpType = "reg";
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let OpType = "reg";
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}
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}
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// These instructions are generated by if conversion. The old value of R1
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// is added as an implicit use.
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class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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RegisterOperand cls2>
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: InstRRF<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$R3),
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mnemonic#"r$R3\t$R1, $R2", []>,
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Requires<[FeatureLoadStoreOnCond]>;
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// Like CondUnaryRRF, but used for the raw assembly form. The condition-code
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// mask is the third operand rather than being part of the mnemonic.
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class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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RegisterOperand cls2>
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: InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, uimm8zx4:$R3),
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mnemonic#"r\t$R1, $R2, $R3", []>,
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Requires<[FeatureLoadStoreOnCond]> {
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let Constraints = "$R1 = $R1src";
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let DisableEncoding = "$R1src";
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}
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// Like CondUnaryRRF, but with a fixed CC mask.
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class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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RegisterOperand cls2, bits<4> ccmask>
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: InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
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mnemonic#"\t$R1, $R2", []>,
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Requires<[FeatureLoadStoreOnCond]> {
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let Constraints = "$R1 = $R1src";
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let DisableEncoding = "$R1src";
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let R3 = ccmask;
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}
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class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
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class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
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RegisterOperand cls, Immediate imm>
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RegisterOperand cls, Immediate imm>
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: InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
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: InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
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@ -277,6 +277,58 @@ SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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return Count;
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return Count;
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}
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}
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// If Opcode is a move that has a conditional variant, return that variant,
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// otherwise return 0.
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static unsigned getConditionalMove(unsigned Opcode) {
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switch (Opcode) {
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case SystemZ::LR: return SystemZ::LOCR;
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case SystemZ::LGR: return SystemZ::LOCGR;
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default: return 0;
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}
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}
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bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
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unsigned Opcode = MI->getOpcode();
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if (TM.getSubtargetImpl()->hasLoadStoreOnCond() &&
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getConditionalMove(Opcode))
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return true;
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return false;
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}
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bool SystemZInstrInfo::
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isProfitableToIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles, unsigned ExtraPredCycles,
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const BranchProbability &Probability) const {
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// For now only convert single instructions.
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return NumCycles == 1;
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}
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bool SystemZInstrInfo::
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isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumCyclesT, unsigned ExtraPredCyclesT,
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MachineBasicBlock &FMBB,
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unsigned NumCyclesF, unsigned ExtraPredCyclesF,
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const BranchProbability &Probability) const {
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// For now avoid converting mutually-exclusive cases.
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return false;
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}
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bool SystemZInstrInfo::
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PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const {
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unsigned CCMask = Pred[0].getImm();
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assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
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unsigned Opcode = MI->getOpcode();
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if (TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
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if (unsigned CondOpcode = getConditionalMove(Opcode)) {
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MI->setDesc(get(CondOpcode));
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MachineInstrBuilder(*MI->getParent()->getParent(), MI).addImm(CCMask);
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return true;
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}
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}
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return false;
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}
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void
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void
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SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc DL,
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MachineBasicBlock::iterator MBBI, DebugLoc DL,
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@ -104,6 +104,23 @@ public:
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MachineBasicBlock *FBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const LLVM_OVERRIDE;
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DebugLoc DL) const LLVM_OVERRIDE;
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virtual bool isPredicable(MachineInstr *MI) const LLVM_OVERRIDE;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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unsigned ExtraPredCycles,
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const BranchProbability &Probability) const
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LLVM_OVERRIDE;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumCyclesT,
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unsigned ExtraPredCyclesT,
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MachineBasicBlock &FMBB,
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unsigned NumCyclesF,
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unsigned ExtraPredCyclesF,
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const BranchProbability &Probability) const
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LLVM_OVERRIDE;
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virtual bool
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PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const
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LLVM_OVERRIDE;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc DL,
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MachineBasicBlock::iterator MBBI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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@ -112,6 +112,8 @@ multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
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def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
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def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
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"jg"##name##"\t$I2", []>;
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"jg"##name##"\t$I2", []>;
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}
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}
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def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>;
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def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
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def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>;
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def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>;
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def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>;
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def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>;
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def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>;
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def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>;
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@ -225,6 +227,16 @@ let neverHasSideEffects = 1 in {
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def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
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def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
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}
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}
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// Move on condition.
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let isCodeGenOnly = 1, Uses = [CC] in {
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def LOCR : CondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
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def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
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}
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let Uses = [CC] in {
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def AsmLOCR : AsmCondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
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def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
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}
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// Immediate moves.
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// Immediate moves.
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let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
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let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
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isReMaterializable = 1 in {
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isReMaterializable = 1 in {
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@ -48,6 +48,7 @@ public:
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}
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}
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virtual bool addInstSelector() LLVM_OVERRIDE;
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virtual bool addInstSelector() LLVM_OVERRIDE;
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virtual bool addPreSched2() LLVM_OVERRIDE;
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virtual bool addPreEmitPass() LLVM_OVERRIDE;
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virtual bool addPreEmitPass() LLVM_OVERRIDE;
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};
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};
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} // end anonymous namespace
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} // end anonymous namespace
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@ -57,6 +58,12 @@ bool SystemZPassConfig::addInstSelector() {
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return false;
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return false;
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}
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}
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bool SystemZPassConfig::addPreSched2() {
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if (getSystemZTargetMachine().getSubtargetImpl()->hasLoadStoreOnCond())
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addPass(&IfConverterID);
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return true;
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}
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bool SystemZPassConfig::addPreEmitPass() {
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bool SystemZPassConfig::addPreEmitPass() {
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addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
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addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
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return true;
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return true;
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25
test/CodeGen/SystemZ/cond-move-01.ll
Normal file
25
test/CodeGen/SystemZ/cond-move-01.ll
Normal file
@ -0,0 +1,25 @@
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; Test LOCR and LOCGR.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
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; Test LOCR.
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define i32 @f1(i32 %a, i32 %b, i32 %limit) {
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; CHECK-LABEL: f1:
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; CHECK: clfi %r4, 42
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; CHECK: locrnl %r2, %r3
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%res = select i1 %cond, i32 %a, i32 %b
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ret i32 %res
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}
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; Test LOCGR.
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define i64 @f2(i64 %a, i64 %b, i64 %limit) {
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; CHECK-LABEL: f2:
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; CHECK: clgfi %r4, 42
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; CHECK: locgrnl %r2, %r3
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; CHECK: br %r14
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%cond = icmp ult i64 %limit, 42
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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@ -3358,6 +3358,102 @@
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# CHECK: locg %r7, 6399(%r8), 15
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# CHECK: locg %r7, 6399(%r8), 15
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0xeb 0x7f 0x88 0xff 0x01 0xe2
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0xeb 0x7f 0x88 0xff 0x01 0xe2
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# CHECK: locr %r11, %r3, 0
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0xb9 0xf2 0x00 0xb3
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# CHECK: locro %r11, %r3
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0xb9 0xf2 0x10 0xb3
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# CHECK: locrh %r11, %r3
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0xb9 0xf2 0x20 0xb3
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# CHECK: locrnle %r11, %r3
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0xb9 0xf2 0x30 0xb3
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# CHECK: locrl %r11, %r3
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0xb9 0xf2 0x40 0xb3
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# CHECK: locrnhe %r11, %r3
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0xb9 0xf2 0x50 0xb3
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# CHECK: locrlh %r11, %r3
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0xb9 0xf2 0x60 0xb3
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# CHECK: locrne %r11, %r3
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0xb9 0xf2 0x70 0xb3
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# CHECK: locre %r11, %r3
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0xb9 0xf2 0x80 0xb3
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# CHECK: locrnlh %r11, %r3
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0xb9 0xf2 0x90 0xb3
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# CHECK: locrhe %r11, %r3
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0xb9 0xf2 0xa0 0xb3
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# CHECK: locrnl %r11, %r3
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0xb9 0xf2 0xb0 0xb3
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# CHECK: locrle %r11, %r3
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0xb9 0xf2 0xc0 0xb3
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# CHECK: locrnh %r11, %r3
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0xb9 0xf2 0xd0 0xb3
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# CHECK: locrno %r11, %r3
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0xb9 0xf2 0xe0 0xb3
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# CHECK: locr %r11, %r3, 15
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0xb9 0xf2 0xf0 0xb3
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# CHECK: locgr %r11, %r3, 0
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0xb9 0xe2 0x00 0xb3
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# CHECK: locgro %r11, %r3
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0xb9 0xe2 0x10 0xb3
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# CHECK: locgrh %r11, %r3
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0xb9 0xe2 0x20 0xb3
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# CHECK: locgrnle %r11, %r3
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0xb9 0xe2 0x30 0xb3
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# CHECK: locgrl %r11, %r3
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0xb9 0xe2 0x40 0xb3
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# CHECK: locgrnhe %r11, %r3
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0xb9 0xe2 0x50 0xb3
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# CHECK: locgrlh %r11, %r3
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0xb9 0xe2 0x60 0xb3
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# CHECK: locgrne %r11, %r3
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0xb9 0xe2 0x70 0xb3
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# CHECK: locgre %r11, %r3
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0xb9 0xe2 0x80 0xb3
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# CHECK: locgrnlh %r11, %r3
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0xb9 0xe2 0x90 0xb3
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# CHECK: locgrhe %r11, %r3
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0xb9 0xe2 0xa0 0xb3
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# CHECK: locgrnl %r11, %r3
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0xb9 0xe2 0xb0 0xb3
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# CHECK: locgrle %r11, %r3
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0xb9 0xe2 0xc0 0xb3
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# CHECK: locgrnh %r11, %r3
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0xb9 0xe2 0xd0 0xb3
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# CHECK: locgrno %r11, %r3
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0xb9 0xe2 0xe0 0xb3
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# CHECK: locgr %r11, %r3, 15
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0xb9 0xe2 0xf0 0xb3
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# CHECK: lpdbr %f0, %f9
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# CHECK: lpdbr %f0, %f9
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0xb3 0x10 0x00 0x09
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0xb3 0x10 0x00 0x09
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@ -58,6 +58,22 @@
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locg %r0,524288,1
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locg %r0,524288,1
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locg %r0,0(%r1,%r2),1
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locg %r0,0(%r1,%r2),1
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#CHECK: error: invalid operand
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#CHECK: locgr %r0,%r0,-1
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#CHECK: error: invalid operand
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#CHECK: locgr %r0,%r0,16
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locgr %r0,%r0,-1
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locgr %r0,%r0,16
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#CHECK: error: invalid operand
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#CHECK: locr %r0,%r0,-1
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#CHECK: error: invalid operand
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#CHECK: locr %r0,%r0,16
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locr %r0,%r0,-1
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locr %r0,%r0,16
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#CHECK: error: invalid operand
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#CHECK: error: invalid operand
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#CHECK: sllk %r0,%r0,-524289
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#CHECK: sllk %r0,%r0,-524289
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#CHECK: error: invalid operand
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#CHECK: error: invalid operand
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@ -217,6 +217,78 @@
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locgnh %r1,2(%r3)
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locgnh %r1,2(%r3)
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locgno %r1,2(%r3)
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locgno %r1,2(%r3)
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#CHECK: locgr %r1, %r2, 0 # encoding: [0xb9,0xe2,0x00,0x12]
|
||||||
|
#CHECK: locgr %r1, %r2, 15 # encoding: [0xb9,0xe2,0xf0,0x12]
|
||||||
|
|
||||||
|
locgr %r1,%r2,0
|
||||||
|
locgr %r1,%r2,15
|
||||||
|
|
||||||
|
#CHECK: locgro %r1, %r3 # encoding: [0xb9,0xe2,0x10,0x13]
|
||||||
|
#CHECK: locgrh %r1, %r3 # encoding: [0xb9,0xe2,0x20,0x13]
|
||||||
|
#CHECK: locgrnle %r1, %r3 # encoding: [0xb9,0xe2,0x30,0x13]
|
||||||
|
#CHECK: locgrl %r1, %r3 # encoding: [0xb9,0xe2,0x40,0x13]
|
||||||
|
#CHECK: locgrnhe %r1, %r3 # encoding: [0xb9,0xe2,0x50,0x13]
|
||||||
|
#CHECK: locgrlh %r1, %r3 # encoding: [0xb9,0xe2,0x60,0x13]
|
||||||
|
#CHECK: locgrne %r1, %r3 # encoding: [0xb9,0xe2,0x70,0x13]
|
||||||
|
#CHECK: locgre %r1, %r3 # encoding: [0xb9,0xe2,0x80,0x13]
|
||||||
|
#CHECK: locgrnlh %r1, %r3 # encoding: [0xb9,0xe2,0x90,0x13]
|
||||||
|
#CHECK: locgrhe %r1, %r3 # encoding: [0xb9,0xe2,0xa0,0x13]
|
||||||
|
#CHECK: locgrnl %r1, %r3 # encoding: [0xb9,0xe2,0xb0,0x13]
|
||||||
|
#CHECK: locgrle %r1, %r3 # encoding: [0xb9,0xe2,0xc0,0x13]
|
||||||
|
#CHECK: locgrnh %r1, %r3 # encoding: [0xb9,0xe2,0xd0,0x13]
|
||||||
|
#CHECK: locgrno %r1, %r3 # encoding: [0xb9,0xe2,0xe0,0x13]
|
||||||
|
|
||||||
|
locgro %r1,%r3
|
||||||
|
locgrh %r1,%r3
|
||||||
|
locgrnle %r1,%r3
|
||||||
|
locgrl %r1,%r3
|
||||||
|
locgrnhe %r1,%r3
|
||||||
|
locgrlh %r1,%r3
|
||||||
|
locgrne %r1,%r3
|
||||||
|
locgre %r1,%r3
|
||||||
|
locgrnlh %r1,%r3
|
||||||
|
locgrhe %r1,%r3
|
||||||
|
locgrnl %r1,%r3
|
||||||
|
locgrle %r1,%r3
|
||||||
|
locgrnh %r1,%r3
|
||||||
|
locgrno %r1,%r3
|
||||||
|
|
||||||
|
#CHECK: locr %r1, %r2, 0 # encoding: [0xb9,0xf2,0x00,0x12]
|
||||||
|
#CHECK: locr %r1, %r2, 15 # encoding: [0xb9,0xf2,0xf0,0x12]
|
||||||
|
|
||||||
|
locr %r1,%r2,0
|
||||||
|
locr %r1,%r2,15
|
||||||
|
|
||||||
|
#CHECK: locro %r1, %r3 # encoding: [0xb9,0xf2,0x10,0x13]
|
||||||
|
#CHECK: locrh %r1, %r3 # encoding: [0xb9,0xf2,0x20,0x13]
|
||||||
|
#CHECK: locrnle %r1, %r3 # encoding: [0xb9,0xf2,0x30,0x13]
|
||||||
|
#CHECK: locrl %r1, %r3 # encoding: [0xb9,0xf2,0x40,0x13]
|
||||||
|
#CHECK: locrnhe %r1, %r3 # encoding: [0xb9,0xf2,0x50,0x13]
|
||||||
|
#CHECK: locrlh %r1, %r3 # encoding: [0xb9,0xf2,0x60,0x13]
|
||||||
|
#CHECK: locrne %r1, %r3 # encoding: [0xb9,0xf2,0x70,0x13]
|
||||||
|
#CHECK: locre %r1, %r3 # encoding: [0xb9,0xf2,0x80,0x13]
|
||||||
|
#CHECK: locrnlh %r1, %r3 # encoding: [0xb9,0xf2,0x90,0x13]
|
||||||
|
#CHECK: locrhe %r1, %r3 # encoding: [0xb9,0xf2,0xa0,0x13]
|
||||||
|
#CHECK: locrnl %r1, %r3 # encoding: [0xb9,0xf2,0xb0,0x13]
|
||||||
|
#CHECK: locrle %r1, %r3 # encoding: [0xb9,0xf2,0xc0,0x13]
|
||||||
|
#CHECK: locrnh %r1, %r3 # encoding: [0xb9,0xf2,0xd0,0x13]
|
||||||
|
#CHECK: locrno %r1, %r3 # encoding: [0xb9,0xf2,0xe0,0x13]
|
||||||
|
|
||||||
|
locro %r1,%r3
|
||||||
|
locrh %r1,%r3
|
||||||
|
locrnle %r1,%r3
|
||||||
|
locrl %r1,%r3
|
||||||
|
locrnhe %r1,%r3
|
||||||
|
locrlh %r1,%r3
|
||||||
|
locrne %r1,%r3
|
||||||
|
locre %r1,%r3
|
||||||
|
locrnlh %r1,%r3
|
||||||
|
locrhe %r1,%r3
|
||||||
|
locrnl %r1,%r3
|
||||||
|
locrle %r1,%r3
|
||||||
|
locrnh %r1,%r3
|
||||||
|
locrno %r1,%r3
|
||||||
|
|
||||||
#CHECK: ngrk %r0, %r0, %r0 # encoding: [0xb9,0xe4,0x00,0x00]
|
#CHECK: ngrk %r0, %r0, %r0 # encoding: [0xb9,0xe4,0x00,0x00]
|
||||||
#CHECK: ngrk %r0, %r0, %r15 # encoding: [0xb9,0xe4,0xf0,0x00]
|
#CHECK: ngrk %r0, %r0, %r15 # encoding: [0xb9,0xe4,0xf0,0x00]
|
||||||
#CHECK: ngrk %r0, %r15, %r0 # encoding: [0xb9,0xe4,0x00,0x0f]
|
#CHECK: ngrk %r0, %r15, %r0 # encoding: [0xb9,0xe4,0x00,0x0f]
|
||||||
|
Loading…
Reference in New Issue
Block a user