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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-28 06:32:09 +00:00
refactor GetRegistersForValue to take OpInfo as an argument instead of various
pieces of it. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36592 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
3ff90dc1c8
commit
bf996f1d5e
@ -82,6 +82,8 @@ namespace {
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createDefaultScheduler);
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} // namespace
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namespace { struct AsmOperandInfo; }
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namespace {
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/// RegsForValue - This struct represents the physical registers that a
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/// particular value is assigned and the type information about the value.
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@ -516,8 +518,7 @@ public:
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N = NewN;
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}
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RegsForValue GetRegistersForValue(const std::string &ConstrCode,
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MVT::ValueType VT,
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RegsForValue GetRegistersForValue(AsmOperandInfo &OpInfo,
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bool OutReg, bool InReg,
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std::set<unsigned> &OutputRegs,
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std::set<unsigned> &InputRegs);
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@ -3013,126 +3014,6 @@ isAllocatableRegister(unsigned Reg, MachineFunction &MF,
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return FoundRC;
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}
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RegsForValue SelectionDAGLowering::
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GetRegistersForValue(const std::string &ConstrCode,
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MVT::ValueType VT, bool isOutReg, bool isInReg,
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std::set<unsigned> &OutputRegs,
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std::set<unsigned> &InputRegs) {
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std::pair<unsigned, const TargetRegisterClass*> PhysReg =
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TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
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std::vector<unsigned> Regs;
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unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
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MVT::ValueType RegVT;
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MVT::ValueType ValueVT = VT;
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// If this is a constraint for a specific physical register, like {r17},
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// assign it now.
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if (PhysReg.first) {
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if (VT == MVT::Other)
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ValueVT = *PhysReg.second->vt_begin();
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// Get the actual register value type. This is important, because the user
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// may have asked for (e.g.) the AX register in i32 type. We need to
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// remember that AX is actually i16 to get the right extension.
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RegVT = *PhysReg.second->vt_begin();
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// This is a explicit reference to a physical register.
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Regs.push_back(PhysReg.first);
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// If this is an expanded reference, add the rest of the regs to Regs.
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if (NumRegs != 1) {
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TargetRegisterClass::iterator I = PhysReg.second->begin();
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TargetRegisterClass::iterator E = PhysReg.second->end();
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for (; *I != PhysReg.first; ++I)
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assert(I != E && "Didn't find reg!");
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// Already added the first reg.
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--NumRegs; ++I;
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for (; NumRegs; --NumRegs, ++I) {
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assert(I != E && "Ran out of registers to allocate!");
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Regs.push_back(*I);
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}
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}
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return RegsForValue(Regs, RegVT, ValueVT);
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}
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// Otherwise, if this was a reference to an LLVM register class, create vregs
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// for this reference.
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std::vector<unsigned> RegClassRegs;
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if (PhysReg.second) {
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// If this is an early clobber or tied register, our regalloc doesn't know
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// how to maintain the constraint. If it isn't, go ahead and create vreg
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// and let the regalloc do the right thing.
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if (!isOutReg || !isInReg) {
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RegVT = *PhysReg.second->vt_begin();
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if (VT == MVT::Other)
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ValueVT = RegVT;
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// Create the appropriate number of virtual registers.
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SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
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for (; NumRegs; --NumRegs)
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Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
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return RegsForValue(Regs, RegVT, ValueVT);
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}
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// Otherwise, we can't allocate it. Let the code below figure out how to
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// maintain these constraints.
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RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
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} else {
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// This is a reference to a register class that doesn't directly correspond
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// to an LLVM register class. Allocate NumRegs consecutive, available,
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// registers from the class.
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RegClassRegs = TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
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}
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const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
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MachineFunction &MF = *CurMBB->getParent();
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unsigned NumAllocated = 0;
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for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
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unsigned Reg = RegClassRegs[i];
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// See if this register is available.
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if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
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(isInReg && InputRegs.count(Reg))) { // Already used.
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// Make sure we find consecutive registers.
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NumAllocated = 0;
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continue;
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}
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// Check to see if this register is allocatable (i.e. don't give out the
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// stack pointer).
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const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
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if (!RC) {
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// Make sure we find consecutive registers.
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NumAllocated = 0;
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continue;
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}
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// Okay, this register is good, we can use it.
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++NumAllocated;
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// If we allocated enough consecutive registers, succeed.
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if (NumAllocated == NumRegs) {
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unsigned RegStart = (i-NumAllocated)+1;
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unsigned RegEnd = i+1;
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// Mark all of the allocated registers used.
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for (unsigned i = RegStart; i != RegEnd; ++i) {
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unsigned Reg = RegClassRegs[i];
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Regs.push_back(Reg);
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if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
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if (isInReg) InputRegs.insert(Reg); // Mark reg used.
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}
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return RegsForValue(Regs, *RC->vt_begin(), VT);
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}
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}
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// Otherwise, we couldn't allocate enough registers for this.
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return RegsForValue();
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}
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namespace {
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/// AsmOperandInfo - This contains information for each constraint that we are
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@ -3212,6 +3093,131 @@ void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
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}
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RegsForValue SelectionDAGLowering::
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GetRegistersForValue(AsmOperandInfo &OpInfo, bool isOutReg, bool isInReg,
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std::set<unsigned> &OutputRegs,
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std::set<unsigned> &InputRegs) {
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std::pair<unsigned, const TargetRegisterClass*> PhysReg =
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TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,OpInfo.ConstraintVT);
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std::vector<unsigned> Regs;
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unsigned NumRegs = 1;
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if (OpInfo.ConstraintVT != MVT::Other)
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NumRegs = TLI.getNumElements(OpInfo.ConstraintVT);
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MVT::ValueType RegVT;
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MVT::ValueType ValueVT = OpInfo.ConstraintVT;
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MachineFunction &MF = DAG.getMachineFunction();
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// If this is a constraint for a specific physical register, like {r17},
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// assign it now.
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if (PhysReg.first) {
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if (OpInfo.ConstraintVT == MVT::Other)
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ValueVT = *PhysReg.second->vt_begin();
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// Get the actual register value type. This is important, because the user
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// may have asked for (e.g.) the AX register in i32 type. We need to
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// remember that AX is actually i16 to get the right extension.
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RegVT = *PhysReg.second->vt_begin();
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// This is a explicit reference to a physical register.
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Regs.push_back(PhysReg.first);
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// If this is an expanded reference, add the rest of the regs to Regs.
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if (NumRegs != 1) {
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TargetRegisterClass::iterator I = PhysReg.second->begin();
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TargetRegisterClass::iterator E = PhysReg.second->end();
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for (; *I != PhysReg.first; ++I)
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assert(I != E && "Didn't find reg!");
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// Already added the first reg.
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--NumRegs; ++I;
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for (; NumRegs; --NumRegs, ++I) {
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assert(I != E && "Ran out of registers to allocate!");
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Regs.push_back(*I);
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}
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}
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return RegsForValue(Regs, RegVT, ValueVT);
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}
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// Otherwise, if this was a reference to an LLVM register class, create vregs
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// for this reference.
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std::vector<unsigned> RegClassRegs;
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if (PhysReg.second) {
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// If this is an early clobber or tied register, our regalloc doesn't know
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// how to maintain the constraint. If it isn't, go ahead and create vreg
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// and let the regalloc do the right thing.
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if (!isOutReg || !isInReg) {
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RegVT = *PhysReg.second->vt_begin();
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if (OpInfo.ConstraintVT == MVT::Other)
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ValueVT = RegVT;
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// Create the appropriate number of virtual registers.
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SSARegMap *RegMap = MF.getSSARegMap();
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for (; NumRegs; --NumRegs)
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Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
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return RegsForValue(Regs, RegVT, ValueVT);
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}
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// Otherwise, we can't allocate it. Let the code below figure out how to
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// maintain these constraints.
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RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
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} else {
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// This is a reference to a register class that doesn't directly correspond
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// to an LLVM register class. Allocate NumRegs consecutive, available,
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// registers from the class.
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RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
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OpInfo.ConstraintVT);
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}
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const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
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unsigned NumAllocated = 0;
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for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
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unsigned Reg = RegClassRegs[i];
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// See if this register is available.
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if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
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(isInReg && InputRegs.count(Reg))) { // Already used.
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// Make sure we find consecutive registers.
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NumAllocated = 0;
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continue;
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}
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// Check to see if this register is allocatable (i.e. don't give out the
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// stack pointer).
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const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
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if (!RC) {
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// Make sure we find consecutive registers.
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NumAllocated = 0;
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continue;
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}
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// Okay, this register is good, we can use it.
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++NumAllocated;
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// If we allocated enough consecutive registers, succeed.
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if (NumAllocated == NumRegs) {
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unsigned RegStart = (i-NumAllocated)+1;
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unsigned RegEnd = i+1;
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// Mark all of the allocated registers used.
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for (unsigned i = RegStart; i != RegEnd; ++i) {
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unsigned Reg = RegClassRegs[i];
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Regs.push_back(Reg);
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if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
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if (isInReg) InputRegs.insert(Reg); // Mark reg used.
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}
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return RegsForValue(Regs, *RC->vt_begin(), OpInfo.ConstraintVT);
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}
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}
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// Otherwise, we couldn't allocate enough registers for this.
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return RegsForValue();
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}
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/// visitInlineAsm - Handle a call to an InlineAsm object.
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///
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void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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@ -3336,8 +3342,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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// Build a list of regs that this operand uses. This always has a single
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// element for promoted/expanded operands.
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RegsForValue Regs = GetRegistersForValue(OpInfo.ConstraintCode, OpVT,
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false, false,
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RegsForValue Regs = GetRegistersForValue(OpInfo, false, false,
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OutputRegs, InputRegs);
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switch (OpInfo.Type) {
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@ -3407,8 +3412,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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// Copy the output from the appropriate register. Find a register that
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// we can use.
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RegsForValue Regs =
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GetRegistersForValue(OpInfo.ConstraintCode, OpInfo.ConstraintVT,
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true, UsesInputRegister,
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GetRegistersForValue(OpInfo, true, UsesInputRegister,
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OutputRegs, InputRegs);
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if (Regs.Regs.empty()) {
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cerr << "Couldn't allocate output reg for contraint '"
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@ -3515,8 +3519,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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// Copy the input into the appropriate registers.
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RegsForValue InRegs =
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GetRegistersForValue(OpInfo.ConstraintCode, OpInfo.ConstraintVT,
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false, true, OutputRegs, InputRegs);
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GetRegistersForValue(OpInfo, false, true, OutputRegs, InputRegs);
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// FIXME: should be match fail.
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assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
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@ -3527,8 +3530,8 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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}
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case InlineAsm::isClobber: {
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RegsForValue ClobberedRegs =
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GetRegistersForValue(OpInfo.ConstraintCode, MVT::Other, false, false,
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OutputRegs, InputRegs);
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GetRegistersForValue(OpInfo, false,
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false, OutputRegs, InputRegs);
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// Add the clobbered value to the operand list, so that the register
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// allocator is aware that the physreg got clobbered.
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if (!ClobberedRegs.Regs.empty())
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