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R600/SI: Fix another case of illegal VGPR->SGPR copy

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195025 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-11-18 18:50:15 +00:00
parent 7c5498ee55
commit bf9ddd5e8f
2 changed files with 28 additions and 3 deletions
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5
lib/Target/R600/SIFixSGPRCopies.cpp
View File

@ -181,14 +181,13 @@ bool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy,
unsigned SrcReg = Copy.getOperand(1).getReg();
unsigned SrcSubReg = Copy.getOperand(1).getSubReg();
const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
const TargetRegisterClass *SrcRC;
if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
DstRC == &AMDGPU::M0RegRegClass)
return false;
const TargetRegisterClass *SrcRC = TRI->getSubRegClass(
MRI.getRegClass(SrcReg), SrcSubReg);
SrcRC = inferRegClassFromDef(TRI, MRI, SrcReg, SrcSubReg);
return TRI->isSGPRClass(DstRC) &&
!TRI->getCommonSubClass(DstRC, SrcRC);
}

26
test/CodeGen/R600/sgpr-copy.ll
View File

@ -268,3 +268,29 @@ endif:
}
!2 = metadata !{metadata !"const", null, i32 1}
; CHECK-LABEL: @copy1
; CHECK: BUFFER_LOAD_DWORD
; CHECK: V_ADD
; CHECK: S_ENDPGM
define void @copy1(float addrspace(1)* %out, float addrspace(1)* %in0) {
entry:
%0 = load float addrspace(1)* %in0
%1 = fcmp oeq float %0, 0.0
br i1 %1, label %if0, label %endif
if0:
%2 = bitcast float %0 to i32
%3 = fcmp olt float %0, 0.0
br i1 %3, label %if1, label %endif
if1:
%4 = add i32 %2, 1
br label %endif
endif:
%5 = phi i32 [ 0, %entry ], [ %2, %if0 ], [ %4, %if1 ]
%6 = bitcast i32 %5 to float
store float %6, float addrspace(1)* %out
ret void
}