From c0578c36bb11ae80947fba66efe4b14df7c4027b Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Wed, 8 Apr 2015 01:09:22 +0000 Subject: [PATCH] R600/SI: Add missing SOPK instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234380 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIInstrFormats.td | 13 +++++++++ lib/Target/R600/SIInstrInfo.td | 44 ++++++++++++++++++++++++++++--- lib/Target/R600/SIInstructions.td | 28 +++++++++++++------- 3 files changed, 72 insertions(+), 13 deletions(-) diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td index 4167590360d..e7a07a16926 100644 --- a/lib/Target/R600/SIInstrFormats.td +++ b/lib/Target/R600/SIInstrFormats.td @@ -181,6 +181,19 @@ class SOPKe op> : Enc32 { let Inst{31-28} = 0xb; //encoding } +class SOPK64e op> : Enc64 { + bits <7> sdst = 0; + bits <16> simm16; + bits <32> imm; + + let Inst{15-0} = simm16; + let Inst{22-16} = sdst; + let Inst{27-23} = op; + let Inst{31-28} = 0xb; + + let Inst{63-32} = imm; +} + class SOPPe op> : Enc32 { bits <16> simm16; diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 866e3490cc0..ebf4f392a44 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -547,6 +547,16 @@ class SOPK_Real_vi : SOPKe , SIMCInstr; +multiclass SOPK_m { + def "" : SOPK_Pseudo ; + + def _si : SOPK_Real_si ; + + def _vi : SOPK_Real_vi ; + +} + multiclass SOPK_32 pattern> { def "" : SOPK_Pseudo ; @@ -562,13 +572,39 @@ multiclass SOPK_SCC pattern> { def "" : SOPK_Pseudo ; - def _si : SOPK_Real_si ; + let DisableEncoding = "$dst" in { + def _si : SOPK_Real_si ; - def _vi : SOPK_Real_vi ; + def _vi : SOPK_Real_vi ; + } } +multiclass SOPK_32TIE pattern> : SOPK_m < + op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16), + " $sdst, $simm16" +>; + +multiclass SOPK_IMM32 { + + def "" : SOPK_Pseudo ; + + def _si : SOPK , + SOPK64e , + SIMCInstr { + let AssemblerPredicates = [isSICI]; + let isCodeGenOnly = 0; + } + + def _vi : SOPK , + SOPK64e , + SIMCInstr { + let AssemblerPredicates = [isVI]; + let isCodeGenOnly = 0; + } +} //===----------------------------------------------------------------------===// // SMRD classes //===----------------------------------------------------------------------===// diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 95b2470273c..9ee0e80489e 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -387,6 +387,7 @@ defm S_CMPK_EQ_I32 : SOPK_SCC , "s_cmpk_eq_i32", >; */ +defm S_CMPK_EQ_I32 : SOPK_SCC , "s_cmpk_eq_i32", []>; defm S_CMPK_LG_I32 : SOPK_SCC , "s_cmpk_lg_i32", []>; defm S_CMPK_GT_I32 : SOPK_SCC , "s_cmpk_gt_i32", []>; defm S_CMPK_GE_I32 : SOPK_SCC , "s_cmpk_ge_i32", []>; @@ -400,18 +401,27 @@ defm S_CMPK_LT_U32 : SOPK_SCC , "s_cmpk_lt_u32", []>; defm S_CMPK_LE_U32 : SOPK_SCC , "s_cmpk_le_u32", []>; } // End isCompare = 1 -let isCommutable = 1 in { - let Defs = [SCC], isCommutable = 1 in { - defm S_ADDK_I32 : SOPK_32 , "s_addk_i32", []>; - } - defm S_MULK_I32 : SOPK_32 , "s_mulk_i32", []>; +let Defs = [SCC], isCommutable = 1, DisableEncoding = "$src0", + Constraints = "$sdst = $src0" in { + defm S_ADDK_I32 : SOPK_32TIE , "s_addk_i32", []>; + defm S_MULK_I32 : SOPK_32TIE , "s_mulk_i32", []>; } -//defm S_CBRANCH_I_FORK : SOPK_ , "s_cbranch_i_fork", []>; +defm S_CBRANCH_I_FORK : SOPK_m < + sopk<0x11, 0x10>, "s_cbranch_i_fork", (outs), + (ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16" +>; defm S_GETREG_B32 : SOPK_32 , "s_getreg_b32", []>; -defm S_SETREG_B32 : SOPK_32 , "s_setreg_b32", []>; -defm S_GETREG_REGRD_B32 : SOPK_32 , "s_getreg_regrd_b32", []>; -//defm S_SETREG_IMM32_B32 : SOPK_32 , "s_setreg_imm32_b32", []>; +defm S_SETREG_B32 : SOPK_m < + sopk<0x13, 0x12>, "s_setreg_b32", (outs), + (ins SReg_32:$sdst, u16imm:$simm16), " $sdst, $simm16" +>; +// FIXME: Not on SI? +//defm S_GETREG_REGRD_B32 : SOPK_32 , "s_getreg_regrd_b32", []>; +defm S_SETREG_IMM32_B32 : SOPK_IMM32 < + sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs), + (ins i32imm:$imm, u16imm:$simm16), " $imm, $simm16" +>; //===----------------------------------------------------------------------===// // SOPP Instructions