mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-18 12:29:21 +00:00
Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but
doesn't work right). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28921 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
041e9d345f
commit
c08f902bb7
@ -63,6 +63,18 @@ namespace {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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/// getI64Imm - Return a target constant with the specified value, of type
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/// i64.
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inline SDOperand getI64Imm(uint64_t Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i64);
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}
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/// getSmallIPtrImm - Return a target constant of pointer type.
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inline SDOperand getSmallIPtrImm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
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}
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/// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
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/// base register. Return the virtual register that holds this value.
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SDOperand getGlobalBaseReg();
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@ -111,7 +123,7 @@ namespace {
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case 'o': // offsetable
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if (!SelectAddrImm(Op, Op0, Op1)) {
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Select(Op0, Op); // r+0.
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Op1 = getI32Imm(0);
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Op1 = getSmallIPtrImm(0);
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}
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break;
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case 'v': // not offsetable
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@ -290,26 +302,73 @@ SDOperand PPCDAGToDAGISel::getGlobalBaseReg() {
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MachineBasicBlock &FirstMBB = BB->getParent()->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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SSARegMap *RegMap = BB->getParent()->getSSARegMap();
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// FIXME: when we get to LP64, we will need to create the appropriate
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// type of register here.
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GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
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if (PPCLowering.getPointerTy() == MVT::i32)
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GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
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else
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GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass);
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BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
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BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
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}
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return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
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return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy());
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}
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/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
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/// or 64-bit immediate, and if the value can be accurately represented as a
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/// sign extension from a 16-bit value. If so, this returns true and the
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/// immediate.
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static bool isIntS16Immediate(SDNode *N, short &Imm) {
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if (N->getOpcode() != ISD::Constant)
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return false;
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Imm = (short)cast<ConstantSDNode>(N)->getValue();
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if (N->getValueType(0) == MVT::i32)
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return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
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else
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return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
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}
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static bool isIntS16Immediate(SDOperand Op, short &Imm) {
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return isIntS16Immediate(Op.Val, Imm);
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}
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// isIntImmediate - This method tests to see if a constant operand.
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// If so Imm will receive the 32 bit value.
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static bool isIntImmediate(SDNode *N, unsigned& Imm) {
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if (N->getOpcode() == ISD::Constant) {
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/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
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/// operand. If so Imm will receive the 32-bit value.
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static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
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if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
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Imm = cast<ConstantSDNode>(N)->getValue();
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return true;
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}
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return false;
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}
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/// isInt64Immediate - This method tests to see if the node is a 64-bit constant
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/// operand. If so Imm will receive the 64-bit value.
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static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
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if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
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Imm = cast<ConstantSDNode>(N)->getValue();
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return true;
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}
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return false;
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}
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// isInt32Immediate - This method tests to see if a constant operand.
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// If so Imm will receive the 32 bit value.
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static bool isInt32Immediate(SDOperand N, unsigned &Imm) {
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return isInt32Immediate(N.Val, Imm);
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}
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// isOpcWithIntImmediate - This method tests to see if the node is a specific
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// opcode and that it has a immediate integer right operand.
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// If so Imm will receive the 32 bit value.
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static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
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return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).Val, Imm);
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}
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// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
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// any number of 0s on either side. The 1s are allowed to wrap from LSB to
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// MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
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@ -348,7 +407,7 @@ static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
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unsigned Indeterminant = ~0; // bit mask marking indeterminant results
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unsigned Opcode = N->getOpcode();
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if (N->getNumOperands() != 2 ||
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!isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
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!isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift > 31))
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return false;
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if (Opcode == ISD::SHL) {
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@ -376,23 +435,6 @@ static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
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return false;
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}
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// isOpcWithIntImmediate - This method tests to see if the node is a specific
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// opcode and that it has a immediate integer right operand.
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// If so Imm will receive the 32 bit value.
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static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
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return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
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}
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// isIntImmediate - This method tests to see if a constant operand.
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// If so Imm will receive the 32 bit value.
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static bool isIntImmediate(SDOperand N, unsigned& Imm) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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Imm = (unsigned)CN->getSignExtended();
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return true;
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}
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return false;
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}
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/// SelectBitfieldInsert - turn an or of two masked values into
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/// the rotate left word immediate then mask insert (rlwimi) instruction.
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SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
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@ -440,14 +482,14 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
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bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
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if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
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isIntImmediate(Op1.getOperand(1), Value)) {
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isInt32Immediate(Op1.getOperand(1), Value)) {
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Op1 = Op1.getOperand(0);
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SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
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}
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if (Op1Opc == ISD::AND) {
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unsigned SHOpc = Op1.getOperand(0).getOpcode();
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if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
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isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
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isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
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Op1 = Op1.getOperand(0).getOperand(0);
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SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
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} else {
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@ -475,11 +517,11 @@ bool PPCDAGToDAGISel::SelectAddrImm(SDOperand N, SDOperand &Disp,
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return false;
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if (N.getOpcode() == ISD::ADD) {
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unsigned imm = 0;
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if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
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Disp = getI32Imm(imm & 0xFFFF);
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short imm = 0;
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if (isIntS16Immediate(N.getOperand(1), imm)) {
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Disp = getI32Imm((int)imm & 0xFFFF);
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
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} else {
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Base = N.getOperand(0);
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}
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@ -496,43 +538,48 @@ bool PPCDAGToDAGISel::SelectAddrImm(SDOperand N, SDOperand &Disp,
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return true; // [&g+r]
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}
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} else if (N.getOpcode() == ISD::OR) {
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unsigned imm = 0;
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if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
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short imm = 0;
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if (isIntS16Immediate(N.getOperand(1), imm)) {
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// If this is an or of disjoint bitfields, we can codegen this as an add
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// (for better address arithmetic) if the LHS and RHS of the OR are
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// provably disjoint.
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uint64_t LHSKnownZero, LHSKnownOne;
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PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
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LHSKnownZero, LHSKnownOne);
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if ((LHSKnownZero|~imm) == ~0U) {
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if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
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// If all of the bits are known zero on the LHS or RHS, the add won't
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// carry.
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Base = N.getOperand(0);
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Disp = getI32Imm(imm & 0xFFFF);
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Disp = getI32Imm((int)imm & 0xFFFF);
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return true;
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}
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}
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} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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// Loading from a constant address.
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int Addr = (int)CN->getValue();
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// If this address fits entirely in a 16-bit sext immediate field, codegen
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// this as "d, 0"
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if (Addr == (short)Addr) {
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Disp = getI32Imm(Addr);
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Base = CurDAG->getRegister(PPC::R0, MVT::i32);
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short Imm;
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if (isIntS16Immediate(CN, Imm)) {
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Disp = CurDAG->getTargetConstant(Imm, CN->getValueType(0));
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Base = CurDAG->getRegister(PPC::R0, CN->getValueType(0));
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return true;
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}
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// FIXME: Handle small sext constant offsets in PPC64 mode also!
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if (CN->getValueType(0) == MVT::i32) {
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int Addr = (int)CN->getValue();
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// Otherwise, break this down into an LIS + disp.
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Disp = getI32Imm((short)Addr);
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Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
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return true;
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// Otherwise, break this down into an LIS + disp.
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Disp = getI32Imm((short)Addr);
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Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
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return true;
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}
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}
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Disp = getI32Imm(0);
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Disp = getSmallIPtrImm(0);
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
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else
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Base = N;
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return true; // [r+0]
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@ -543,9 +590,9 @@ bool PPCDAGToDAGISel::SelectAddrImm(SDOperand N, SDOperand &Disp,
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/// be represented by [r+imm], which are preferred.
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bool PPCDAGToDAGISel::SelectAddrIdx(SDOperand N, SDOperand &Base,
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SDOperand &Index) {
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unsigned imm = 0;
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short imm = 0;
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if (N.getOpcode() == ISD::ADD) {
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if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm))
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if (isIntS16Immediate(N.getOperand(1), imm))
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return false; // r+i
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if (N.getOperand(1).getOpcode() == PPCISD::Lo)
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return false; // r+i
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@ -554,7 +601,7 @@ bool PPCDAGToDAGISel::SelectAddrIdx(SDOperand N, SDOperand &Base,
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Index = N.getOperand(1);
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return true;
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} else if (N.getOpcode() == ISD::OR) {
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if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm))
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if (isIntS16Immediate(N.getOperand(1), imm))
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return false; // r+i can fold it if we can.
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// If this is an or of disjoint bitfields, we can codegen this as an add
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@ -601,7 +648,7 @@ bool PPCDAGToDAGISel::SelectAddrIdxOnly(SDOperand N, SDOperand &Base,
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}
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// Otherwise, do it the hard way, using R0 as the base register.
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Base = CurDAG->getRegister(PPC::R0, MVT::i32);
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Base = CurDAG->getRegister(PPC::R0, N.getValueType());
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Index = N;
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return true;
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}
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@ -616,12 +663,11 @@ bool PPCDAGToDAGISel::SelectAddrImmShift(SDOperand N, SDOperand &Disp,
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return false;
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if (N.getOpcode() == ISD::ADD) {
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unsigned imm = 0;
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if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) &&
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(imm & 3) == 0) {
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Disp = getI32Imm((imm & 0xFFFF) >> 2);
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short imm = 0;
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if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
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Disp = getI32Imm(((int)imm & 0xFFFF) >> 2);
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
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} else {
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Base = N.getOperand(0);
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}
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@ -638,34 +684,37 @@ bool PPCDAGToDAGISel::SelectAddrImmShift(SDOperand N, SDOperand &Disp,
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return true; // [&g+r]
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}
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} else if (N.getOpcode() == ISD::OR) {
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unsigned imm = 0;
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if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) &&
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(imm & 3) == 0) {
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short imm = 0;
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if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
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// If this is an or of disjoint bitfields, we can codegen this as an add
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// (for better address arithmetic) if the LHS and RHS of the OR are
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// provably disjoint.
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uint64_t LHSKnownZero, LHSKnownOne;
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PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
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LHSKnownZero, LHSKnownOne);
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if ((LHSKnownZero|~imm) == ~0U) {
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if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
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// If all of the bits are known zero on the LHS or RHS, the add won't
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// carry.
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Base = N.getOperand(0);
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Disp = getI32Imm((imm & 0xFFFF) >> 2);
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Disp = getI32Imm(((int)imm & 0xFFFF) >> 2);
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return true;
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}
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}
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} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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// Loading from a constant address.
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int Addr = (int)CN->getValue();
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if ((Addr & 3) == 0) {
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// If this address fits entirely in a 16-bit sext immediate field, codegen
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// this as "d, 0"
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if (Addr == (short)Addr) {
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Disp = getI32Imm(Addr >> 2);
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Base = CurDAG->getRegister(PPC::R0, MVT::i32);
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return true;
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}
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// If this address fits entirely in a 14-bit sext immediate field, codegen
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// this as "d, 0"
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short Imm;
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if (isIntS16Immediate(CN, Imm)) {
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Disp = getSmallIPtrImm((unsigned short)Imm >> 2);
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Base = CurDAG->getRegister(PPC::R0, CN->getValueType(0));
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return true;
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}
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// FIXME: Handle small sext constant offsets in PPC64 mode also!
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if (CN->getValueType(0) == MVT::i32) {
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int Addr = (int)CN->getValue();
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// Otherwise, break this down into an LIS + disp.
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Disp = getI32Imm((short)Addr >> 2);
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@ -674,9 +723,9 @@ bool PPCDAGToDAGISel::SelectAddrImmShift(SDOperand N, SDOperand &Disp,
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}
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}
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Disp = getI32Imm(0);
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Disp = getSmallIPtrImm(0);
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
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else
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Base = N;
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return true; // [r+0]
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@ -689,25 +738,47 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
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ISD::CondCode CC) {
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// Always select the LHS.
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Select(LHS, LHS);
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// Use U to determine whether the SETCC immediate range is signed or not.
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if (MVT::isInteger(LHS.getValueType())) {
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bool U = ISD::isUnsignedIntSetCC(CC);
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unsigned Imm;
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if (isIntImmediate(RHS, Imm) &&
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((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
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return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI,
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MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0);
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Select(RHS, RHS);
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return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
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LHS, RHS), 0);
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unsigned Opc;
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if (LHS.getValueType() == MVT::i32) {
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unsigned Imm, Opc;
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if (ISD::isUnsignedIntSetCC(CC)) {
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if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
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return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
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getI32Imm(Imm & 0xFFFF)), 0);
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Opc = PPC::CMPLW;
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} else {
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short SImm;
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if (isIntS16Immediate(RHS, SImm))
|
||||
return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
|
||||
getI32Imm((int)SImm & 0xFFFF)),
|
||||
0);
|
||||
Opc = PPC::CMPW;
|
||||
}
|
||||
} else if (LHS.getValueType() == MVT::i64) {
|
||||
uint64_t Imm;
|
||||
unsigned Opc;
|
||||
if (ISD::isUnsignedIntSetCC(CC)) {
|
||||
if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
|
||||
return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
|
||||
getI64Imm(Imm & 0xFFFF)), 0);
|
||||
Opc = PPC::CMPLD;
|
||||
} else {
|
||||
short SImm;
|
||||
if (isIntS16Immediate(RHS, SImm))
|
||||
return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
|
||||
getI64Imm((int)SImm & 0xFFFF)),
|
||||
0);
|
||||
Opc = PPC::CMPD;
|
||||
}
|
||||
} else if (LHS.getValueType() == MVT::f32) {
|
||||
Select(RHS, RHS);
|
||||
return SDOperand(CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, RHS), 0);
|
||||
Opc = PPC::FCMPUS;
|
||||
} else {
|
||||
Select(RHS, RHS);
|
||||
return SDOperand(CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, RHS), 0);
|
||||
assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
|
||||
Opc = PPC::FCMPUD;
|
||||
}
|
||||
Select(RHS, RHS);
|
||||
return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
|
||||
}
|
||||
|
||||
/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
|
||||
@ -774,7 +845,7 @@ SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
|
||||
SDNode *N = Op.Val;
|
||||
unsigned Imm;
|
||||
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
|
||||
if (isIntImmediate(N->getOperand(1), Imm)) {
|
||||
if (isInt32Immediate(N->getOperand(1), Imm)) {
|
||||
// We can codegen setcc op, imm very efficiently compared to a brcond.
|
||||
// Check for those cases here.
|
||||
// setcc op, 0
|
||||
@ -901,16 +972,16 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
|
||||
|
||||
case ISD::FrameIndex: {
|
||||
int FI = cast<FrameIndexSDNode>(N)->getIndex();
|
||||
SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
|
||||
unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
|
||||
if (N->hasOneUse()) {
|
||||
Result = CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
|
||||
CurDAG->getTargetFrameIndex(FI, MVT::i32),
|
||||
getI32Imm(0));
|
||||
Result = CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
|
||||
getSmallIPtrImm(0));
|
||||
return;
|
||||
}
|
||||
Result = CodeGenMap[Op] =
|
||||
SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
|
||||
CurDAG->getTargetFrameIndex(FI, MVT::i32),
|
||||
getI32Imm(0)), 0);
|
||||
SDOperand(CurDAG->getTargetNode(Opc, Op.getValueType(), TFI,
|
||||
getSmallIPtrImm(0)), 0);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -934,7 +1005,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
|
||||
// srl/add/sra pattern the dag combiner will generate for this as
|
||||
// sra/addze rather than having to handle sdiv ourselves. oh well.
|
||||
unsigned Imm;
|
||||
if (isIntImmediate(N->getOperand(1), Imm)) {
|
||||
if (isInt32Immediate(N->getOperand(1), Imm)) {
|
||||
SDOperand N0;
|
||||
Select(N0, N->getOperand(0));
|
||||
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
|
||||
@ -963,8 +1034,8 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
|
||||
unsigned Imm, Imm2;
|
||||
// If this is an and of a value rotated between 0 and 31 bits and then and'd
|
||||
// with a mask, emit rlwinm
|
||||
if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
|
||||
isShiftedMask_32(~Imm))) {
|
||||
if (isInt32Immediate(N->getOperand(1), Imm) &&
|
||||
(isShiftedMask_32(Imm) || isShiftedMask_32(~Imm))) {
|
||||
SDOperand Val;
|
||||
unsigned SH, MB, ME;
|
||||
if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
|
||||
@ -985,9 +1056,9 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
|
||||
}
|
||||
// ISD::OR doesn't get all the bitfield insertion fun.
|
||||
// (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
|
||||
if (isIntImmediate(N->getOperand(1), Imm) &&
|
||||
if (isInt32Immediate(N->getOperand(1), Imm) &&
|
||||
N->getOperand(0).getOpcode() == ISD::OR &&
|
||||
isIntImmediate(N->getOperand(0).getOperand(1), Imm2)) {
|
||||
isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
|
||||
unsigned MB, ME;
|
||||
Imm = ~(Imm^Imm2);
|
||||
if (isRunOfOnes(Imm, MB, ME)) {
|
||||
@ -1046,12 +1117,14 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
|
||||
case ISD::SELECT_CC: {
|
||||
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
|
||||
|
||||
// handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
|
||||
// Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
|
||||
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
|
||||
if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
|
||||
if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
|
||||
if (N1C->isNullValue() && N3C->isNullValue() &&
|
||||
N2C->getValue() == 1ULL && CC == ISD::SETNE) {
|
||||
N2C->getValue() == 1ULL && CC == ISD::SETNE &&
|
||||
// FIXME: Implement this optzn for PPC64.
|
||||
N->getValueType(0) == MVT::i32) {
|
||||
SDOperand LHS;
|
||||
Select(LHS, N->getOperand(0));
|
||||
SDNode *Tmp =
|
||||
@ -1068,8 +1141,10 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
|
||||
|
||||
bool isFP = MVT::isFloatingPoint(N->getValueType(0));
|
||||
unsigned SelectCCOp;
|
||||
if (MVT::isInteger(N->getValueType(0)))
|
||||
SelectCCOp = PPC::SELECT_CC_Int;
|
||||
if (N->getValueType(0) == MVT::i32)
|
||||
SelectCCOp = PPC::SELECT_CC_I4;
|
||||
else if (N->getValueType(0) == MVT::i64)
|
||||
SelectCCOp = PPC::SELECT_CC_I8;
|
||||
else if (N->getValueType(0) == MVT::f32)
|
||||
SelectCCOp = PPC::SELECT_CC_F4;
|
||||
else if (N->getValueType(0) == MVT::f64)
|
||||
@ -1188,8 +1263,10 @@ void PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) {
|
||||
|
||||
Chain = SDOperand(ResNode, 0);
|
||||
InFlag = SDOperand(ResNode, 1);
|
||||
SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val, Chain.ResNo);
|
||||
SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, InFlag.Val, InFlag.ResNo);
|
||||
SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val,
|
||||
Chain.ResNo);
|
||||
SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, InFlag.Val,
|
||||
InFlag.ResNo);
|
||||
Result = SDOperand(ResNode, N.ResNo);
|
||||
return;
|
||||
}
|
||||
@ -1220,8 +1297,10 @@ void PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) {
|
||||
|
||||
Chain = SDOperand(ResNode, 0);
|
||||
InFlag = SDOperand(ResNode, 1);
|
||||
SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val, Chain.ResNo);
|
||||
SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, InFlag.Val, InFlag.ResNo);
|
||||
SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val,
|
||||
Chain.ResNo);
|
||||
SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, InFlag.Val,
|
||||
InFlag.ResNo);
|
||||
Result = SDOperand(ResNode, N.ResNo);
|
||||
return;
|
||||
}
|
||||
@ -1252,8 +1331,10 @@ void PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) {
|
||||
|
||||
Chain = SDOperand(ResNode, 0);
|
||||
InFlag = SDOperand(ResNode, 1);
|
||||
SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val, Chain.ResNo);
|
||||
SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, InFlag.Val, InFlag.ResNo);
|
||||
SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val,
|
||||
Chain.ResNo);
|
||||
SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, InFlag.Val,
|
||||
InFlag.ResNo);
|
||||
Result = SDOperand(ResNode, N.ResNo);
|
||||
return;
|
||||
}
|
||||
|
@ -249,6 +249,7 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
|
||||
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
|
||||
}
|
||||
|
||||
setSetCCResultType(MVT::i32);
|
||||
setSetCCResultContents(ZeroOrOneSetCCResult);
|
||||
setStackPointerRegisterToSaveRestore(PPC::R1);
|
||||
|
||||
@ -2216,7 +2217,8 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
||||
MachineBasicBlock *
|
||||
PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
|
||||
MachineBasicBlock *BB) {
|
||||
assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
|
||||
assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
|
||||
MI->getOpcode() == PPC::SELECT_CC_I8 ||
|
||||
MI->getOpcode() == PPC::SELECT_CC_F4 ||
|
||||
MI->getOpcode() == PPC::SELECT_CC_F8 ||
|
||||
MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
|
||||
|
@ -263,7 +263,9 @@ def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4",
|
||||
// scheduler into a branch sequence.
|
||||
let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
|
||||
PPC970_Single = 1 in {
|
||||
def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
|
||||
def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
|
||||
i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
|
||||
def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F,
|
||||
i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
|
||||
def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
|
||||
i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
|
||||
|
Loading…
Reference in New Issue
Block a user