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Change MachineBasicBlock's vector of MachineInstr pointers into an

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ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11340 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos
2004-02-12 02:27:10 +00:00
parent 918cdd420b
commit c0b9dc5be7
41 changed files with 380 additions and 408 deletions
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12
lib/CodeGen/RegAllocSimple.cpp
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@ -150,12 +150,10 @@ void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// loop over each instruction
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) {
// Made to combat the incorrect allocation of r2 = add r1, r1
std::map<unsigned, unsigned> Virt2PhysRegMap;
MachineInstr *MI = *I;
RegsUsed.resize(MRegisterInfo::FirstVirtualRegister);
// a preliminary pass that will invalidate any registers that
@ -197,11 +195,11 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
} else {
physReg = getFreeReg(virtualReg);
}
++I;
spillVirtReg(MBB, I, virtualReg, physReg);
--I;
++MI;
spillVirtReg(MBB, MI, virtualReg, physReg);
--MI;
} else {
physReg = reloadVirtReg(MBB, I, virtualReg);
physReg = reloadVirtReg(MBB, MI, virtualReg);
Virt2PhysRegMap[virtualReg] = physReg;
}
}