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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 19:55:11 +00:00
temporarily revert the patch due to some conflicts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Weiming Zhao
parent
17fe48ce6e
commit
c0c2816fb3
@ -342,11 +342,6 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
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unsigned Reg = MO.getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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assert(!MO.getSubReg() && "Subregs should be eliminated!");
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if(ARM::GPRPairRegClass.contains(Reg)) {
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const MachineFunction &MF = *MI->getParent()->getParent();
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const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
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Reg = TRI->getSubReg(Reg, ARM::gsub_0);
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}
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O << ARMInstPrinter::getRegisterName(Reg);
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break;
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}
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@ -535,12 +530,14 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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const MachineOperand &MO = MI->getOperand(OpNum);
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if (!MO.isReg())
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return true;
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const TargetRegisterClass &RC = ARM::GPRRegClass;
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const MachineFunction &MF = *MI->getParent()->getParent();
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const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
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unsigned Reg = MO.getReg();
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if(!ARM::GPRPairRegClass.contains(Reg))
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return false;
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Reg = TRI->getSubReg(Reg, ARM::gsub_1);
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unsigned RegIdx = TRI->getEncodingValue(MO.getReg());
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RegIdx |= 1; //The odd register is also the higher-numbered one of a pair.
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unsigned Reg = RC.getRegister(RegIdx);
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O << ARMInstPrinter::getRegisterName(Reg);
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return false;
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}
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@ -19,7 +19,6 @@
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/CallingConv.h"
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@ -258,8 +257,6 @@ private:
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// Select special operations if node forms integer ABS pattern
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SDNode *SelectABSOp(SDNode *N);
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SDNode *SelectInlineAsm(SDNode *N);
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SDNode *SelectConcatVector(SDNode *N);
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SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
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@ -2555,12 +2552,6 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::INLINEASM: {
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SDNode *ResNode = SelectInlineAsm(N);
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if (ResNode)
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return ResNode;
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break;
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}
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case ISD::XOR: {
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// Select special operations if XOR node forms integer ABS pattern
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SDNode *ResNode = SelectABSOp(N);
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@ -3455,138 +3446,6 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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return SelectCode(N);
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}
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SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
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std::vector<SDValue> AsmNodeOperands;
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unsigned Flag, Kind;
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bool Changed = false;
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unsigned NumOps = N->getNumOperands();
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ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(
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N->getOperand(InlineAsm::Op_AsmString));
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StringRef AsmString = StringRef(S->getSymbol());
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// Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
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// However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
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// (even/even+1) GPRs and use %n and %Hn to refer to the individual regs
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// respectively. Since there is no constraint to explicitly specify a
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// reg pair, we search %H operand inside the asm string. If it is found, the
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// transformation below enforces a GPRPair reg class for "%r" for 64-bit data.
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if (AsmString.find(":H}") == StringRef::npos)
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return NULL;
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DebugLoc dl = N->getDebugLoc();
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SDValue Glue = N->getOperand(NumOps-1);
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// Glue node will be appended late.
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for(unsigned i = 0; i < NumOps -1; ++i) {
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SDValue op = N->getOperand(i);
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AsmNodeOperands.push_back(op);
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if (i < InlineAsm::Op_FirstOperand)
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continue;
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
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Flag = C->getZExtValue();
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Kind = InlineAsm::getKind(Flag);
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}
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else
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continue;
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if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
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&& Kind != InlineAsm::Kind_RegDefEarlyClobber)
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continue;
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unsigned RegNum = InlineAsm::getNumOperandRegisters(Flag);
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unsigned RC;
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bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
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if (!HasRC || RC != ARM::GPRRegClassID || RegNum != 2)
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continue;
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assert((i+2 < NumOps-1) && "Invalid number of operands in inline asm");
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SDValue V0 = N->getOperand(i+1);
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SDValue V1 = N->getOperand(i+2);
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unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
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unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
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SDValue PairedReg;
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MachineRegisterInfo &MRI = MF->getRegInfo();
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if (Kind == InlineAsm::Kind_RegDef ||
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Kind == InlineAsm::Kind_RegDefEarlyClobber) {
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// Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
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// the original GPRs.
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unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
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SDValue Chain = SDValue(N,0);
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SDNode *GU = N->getGluedUser();
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SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped,
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Chain.getValue(1));
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// Extract values from a GPRPair reg and copy to the original GPR reg.
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SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
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RegCopy);
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SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
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RegCopy);
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SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
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RegCopy.getValue(1));
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SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
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// Update the original glue user.
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std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
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Ops.push_back(T1.getValue(1));
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CurDAG->UpdateNodeOperands(GU, &Ops[0], Ops.size());
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GU = T1.getNode();
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}
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else {
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// For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
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// GPRPair and then pass the GPRPair to the inline asm.
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SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
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// As REG_SEQ doesn't take RegisterSDNode, we copy them first.
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SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
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Chain.getValue(1));
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SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
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T0.getValue(1));
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SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0);
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// Copy REG_SEQ into a GPRPair-typed VR and replace the original two
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// i32 VRs of inline asm with it.
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unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
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Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
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AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
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Glue = Chain.getValue(1);
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}
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Changed = true;
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if(PairedReg.getNode()) {
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Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
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Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
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// Replace the current flag.
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AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
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Flag, MVT::i32);
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// Add the new register node and skip the original two GPRs.
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AsmNodeOperands.push_back(PairedReg);
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// Skip the next two GPRs.
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i += 2;
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}
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}
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AsmNodeOperands.push_back(Glue);
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if (!Changed)
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return NULL;
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SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
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CurDAG->getVTList(MVT::Other, MVT::Glue), &AsmNodeOperands[0],
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AsmNodeOperands.size());
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New->setNodeId(-1);
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return New.getNode();
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}
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bool ARMDAGToDAGISel::
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SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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std::vector<SDValue> &OutOps) {
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@ -61,7 +61,8 @@ ret void
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define i64 @f4(i64* %val) nounwind {
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entry:
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;CHECK: f4
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;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r0]
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;CHECK: mov r0, [[REG1]]
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%0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(i64* %val, i64* %val) nounwind
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ret i64 %0
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}
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@ -1,54 +0,0 @@
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; RUN: llc < %s -O3 -march=arm | FileCheck %s
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; check if regs are passing correctly
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define void @i64_write(i64* %p, i64 %val) nounwind {
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; CHECK: i64_write:
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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%1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %val) nounwind
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ret void
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}
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; check if register allocation can reuse the registers
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define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind {
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entry:
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; CHECK: multi_writes:
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
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%incdec.ptr = getelementptr inbounds i64* %p, i32 1
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tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
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tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
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ret void
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}
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; check if callee-saved registers used by inline asm are saved/restored
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define void @foo(i64* %p, i64 %i) nounwind {
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; CHECK:foo:
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; CHECK: push {{{r[4-9]|r10|r11}}
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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; CHECK: pop {{{r[4-9]|r10|r11}}
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%1 = tail call { i64, i64 } asm sideeffect "@ atomic64_set\0A1: ldrexd $0, ${0:H}, [$3]\0Aldrexd $1, ${1:H}, [$3]\0A strexd $0, $4, ${4:H}, [$3]\0A teq $0, #0\0A bne 1b", "=&r,=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %i) nounwind
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ret void
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}
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