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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Add methods for querying minimum SSE version along with AVX. Simplifies all the places that had to check a version of SSE and AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145053 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -908,7 +908,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
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}
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if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
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if (Subtarget->hasSSE41orAVX()) {
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setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
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setOperationAction(ISD::FCEIL, MVT::f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
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@ -980,7 +980,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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}
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}
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if (Subtarget->hasSSE42() || Subtarget->hasAVX())
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if (Subtarget->hasSSE42orAVX())
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setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
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if (!UseSoftFloat && Subtarget->hasAVX()) {
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@ -3970,7 +3970,7 @@ static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
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/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
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bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
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const X86Subtarget *Subtarget) {
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if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
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if (!Subtarget->hasSSE3orAVX())
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return false;
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// The second vector must be undef
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@ -3998,7 +3998,7 @@ bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
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/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
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bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
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const X86Subtarget *Subtarget) {
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if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
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if (!Subtarget->hasSSE3orAVX())
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return false;
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// The second vector must be undef
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@ -5509,7 +5509,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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return LD;
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// For SSE 4.1, use insertps to put the high elements into the low element.
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if (getSubtarget()->hasSSE41() || getSubtarget()->hasAVX()) {
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if (getSubtarget()->hasSSE41orAVX()) {
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SDValue Result;
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if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
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Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
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@ -5680,7 +5680,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
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// quads, disable the next transformation since it does not help SSSE3.
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bool V1Used = InputQuads[0] || InputQuads[1];
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bool V2Used = InputQuads[2] || InputQuads[3];
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if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) {
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if (Subtarget->hasSSSE3orAVX()) {
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if (InputQuads.count() == 2 && V1Used && V2Used) {
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BestLoQuad = InputQuads.find_first();
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BestHiQuad = InputQuads.find_next(BestLoQuad);
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@ -5753,7 +5753,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
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// If we have SSSE3, and all words of the result are from 1 input vector,
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// case 2 is generated, otherwise case 3 is generated. If no SSSE3
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// is present, fall back to case 4.
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if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) {
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if (Subtarget->hasSSSE3orAVX()) {
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SmallVector<SDValue,16> pshufbMask;
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// If we have elements from both input vectors, set the high bit of the
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@ -5821,8 +5821,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
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NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
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&MaskV[0]);
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if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE &&
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(Subtarget->hasSSSE3() || Subtarget->hasAVX()))
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if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX())
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NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
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NewV.getOperand(0),
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X86::getShufflePSHUFLWImmediate(NewV.getNode()),
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@ -5850,8 +5849,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
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NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
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&MaskV[0]);
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if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE &&
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(Subtarget->hasSSSE3() || Subtarget->hasAVX()))
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if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX())
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NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
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NewV.getOperand(0),
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X86::getShufflePSHUFHWImmediate(NewV.getNode()),
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@ -5917,7 +5915,7 @@ SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
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}
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// If SSSE3, use 1 pshufb instruction per vector with elements in the result.
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if (TLI.getSubtarget()->hasSSSE3() || TLI.getSubtarget()->hasAVX()) {
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if (TLI.getSubtarget()->hasSSSE3orAVX()) {
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SmallVector<SDValue,16> pshufbMask;
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// If all result elements are from one input vector, then only translate
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@ -6762,8 +6760,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V1,
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DAG);
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if (X86::isMOVDDUPMask(SVOp) &&
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(Subtarget->hasSSE3() || Subtarget->hasAVX()) &&
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if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3orAVX() &&
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V2IsUndef && RelaxedMayFoldVectorLoad(V1))
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return getMOVDDup(Op, dl, V1, DAG);
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@ -6771,7 +6768,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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return getMOVHighToLow(Op, dl, DAG);
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// Use to match splats
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if (HasXMMInt && X86::isUNPCKHMask(SVOp, Subtarget->hasAVX2()) && V2IsUndef &&
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if (HasXMMInt && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef &&
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(VT == MVT::v2f64 || VT == MVT::v2i64))
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return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V1,
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DAG);
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@ -6796,8 +6793,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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bool isLeft = false;
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unsigned ShAmt = 0;
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SDValue ShVal;
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bool isShift = getSubtarget()->hasXMMInt() &&
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isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
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bool isShift = HasXMMInt && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
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if (isShift && ShVal.hasOneUse()) {
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// If the shifted value has multiple uses, it may be cheaper to use
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// v_set0 + movlhps or movhlps, etc.
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@ -6821,8 +6817,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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}
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// FIXME: fold these into legal mask.
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if (X86::isMOVLHPSMask(SVOp) &&
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!X86::isUNPCKLMask(SVOp, Subtarget->hasAVX2()))
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if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2))
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return getMOVLowToHigh(Op, dl, DAG, HasXMMInt);
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if (X86::isMOVHLPSMask(SVOp))
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@ -6875,11 +6870,11 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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return getMOVL(DAG, dl, VT, V2, V1);
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}
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if (X86::isUNPCKLMask(SVOp, Subtarget->hasAVX2()))
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if (X86::isUNPCKLMask(SVOp, HasAVX2))
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return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V2,
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DAG);
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if (X86::isUNPCKHMask(SVOp, Subtarget->hasAVX2()))
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if (X86::isUNPCKHMask(SVOp, HasAVX2))
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return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V2,
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DAG);
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@ -6890,9 +6885,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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SDValue NewMask = NormalizeMask(SVOp, DAG);
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ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
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if (NSVOp != SVOp) {
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if (X86::isUNPCKLMask(NSVOp, Subtarget->hasAVX2(), true)) {
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if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) {
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return NewMask;
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} else if (X86::isUNPCKHMask(NSVOp, Subtarget->hasAVX2(), true)) {
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} else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) {
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return NewMask;
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}
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}
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@ -6904,11 +6899,11 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
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ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
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if (X86::isUNPCKLMask(NewSVOp, Subtarget->hasAVX2()))
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if (X86::isUNPCKLMask(NewSVOp, HasAVX2))
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return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V2, V1,
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DAG);
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if (X86::isUNPCKHMask(NewSVOp, Subtarget->hasAVX2()))
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if (X86::isUNPCKHMask(NewSVOp, HasAVX2))
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return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V2, V1,
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DAG);
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}
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@ -6923,7 +6918,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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SmallVector<int, 16> M;
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SVOp->getMask(M);
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if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX()))
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if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()))
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return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
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X86::getShufflePALIGNRImmediate(SVOp),
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DAG);
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@ -7109,7 +7104,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
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if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
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if (Subtarget->hasSSE41orAVX()) {
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SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
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if (Res.getNode())
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return Res;
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@ -7251,7 +7246,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
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return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
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}
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if (Subtarget->hasSSE41() || Subtarget->hasAVX())
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if (Subtarget->hasSSE41orAVX())
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return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
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if (EltVT == MVT::i8)
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@ -8741,9 +8736,9 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
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// Check that the operation in question is available (most are plain SSE2,
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// but PCMPGTQ and PCMPEQQ have different requirements).
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if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42() && !Subtarget->hasAVX())
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if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42orAVX())
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return SDValue();
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if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41() && !Subtarget->hasAVX())
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if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41orAVX())
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return SDValue();
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// Since SSE has no unsigned integer comparisons, we need to flip the sign
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@ -11403,7 +11398,7 @@ X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
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EVT VT) const {
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// Very little shuffling can be done for 64-bit vectors right now.
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if (VT.getSizeInBits() == 64)
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return isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX());
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return isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX());
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// FIXME: pshufb, blends, shifts.
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return (VT.getVectorNumElements() == 2 ||
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@ -11413,7 +11408,7 @@ X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
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isPSHUFDMask(M, VT) ||
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isPSHUFHWMask(M, VT) ||
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isPSHUFLWMask(M, VT) ||
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isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX()) ||
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isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()) ||
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isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
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isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
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isUNPCKL_v_undef_Mask(M, VT) ||
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@ -11822,7 +11817,7 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
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MachineBasicBlock *
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X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned numArgs, bool memArg) const {
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assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
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assert(Subtarget->hasSSE42orAVX() &&
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"Target must have SSE4.2 or AVX features enabled");
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DebugLoc dl = MI->getDebugLoc();
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@ -13982,7 +13977,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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// look for psign/blend
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if (VT == MVT::v2i64 || VT == MVT::v4i64) {
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if (!(Subtarget->hasSSSE3() || Subtarget->hasAVX()) ||
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if (!Subtarget->hasSSSE3orAVX() ||
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(VT == MVT::v4i64 && !Subtarget->hasAVX2()))
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return SDValue();
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@ -14052,7 +14047,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
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}
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// PBLENDVB only available on SSE 4.1
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if (!(Subtarget->hasSSE41() || Subtarget->hasAVX()))
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if (!Subtarget->hasSSE41orAVX())
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return SDValue();
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EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
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@ -14577,8 +14572,7 @@ static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
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SDValue RHS = N->getOperand(1);
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// Try to synthesize horizontal adds from adds of shuffles.
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if ((Subtarget->hasSSE3() || Subtarget->hasAVX()) &&
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(VT == MVT::v4f32 || VT == MVT::v2f64) &&
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if (Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64) &&
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isHorizontalBinOp(LHS, RHS, true))
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return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
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return SDValue();
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@ -14592,8 +14586,7 @@ static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
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SDValue RHS = N->getOperand(1);
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// Try to synthesize horizontal subs from subs of shuffles.
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if ((Subtarget->hasSSE3() || Subtarget->hasAVX()) &&
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(VT == MVT::v4f32 || VT == MVT::v2f64) &&
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if (Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64) &&
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isHorizontalBinOp(LHS, RHS, false))
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return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
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return SDValue();
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@ -14797,8 +14790,7 @@ static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
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SDValue Op1 = N->getOperand(1);
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// Try to synthesize horizontal adds from adds of shuffles.
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if ((Subtarget->hasSSSE3() || Subtarget->hasAVX()) &&
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(VT == MVT::v8i16 || VT == MVT::v4i32) &&
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if ((Subtarget->hasSSSE3orAVX()) && (VT == MVT::v8i16 || VT == MVT::v4i32) &&
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isHorizontalBinOp(Op0, Op1, true))
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return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
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@ -14830,8 +14822,7 @@ static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
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// Try to synthesize horizontal adds from adds of shuffles.
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EVT VT = N->getValueType(0);
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if ((Subtarget->hasSSSE3() || Subtarget->hasAVX()) &&
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(VT == MVT::v8i16 || VT == MVT::v4i32) &&
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if ((Subtarget->hasSSSE3orAVX()) && (VT == MVT::v8i16 || VT == MVT::v4i32) &&
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isHorizontalBinOp(Op0, Op1, false))
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return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
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@ -190,6 +190,10 @@ public:
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bool hasAVX2() const { return HasAVX2; }
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bool hasXMM() const { return hasSSE1() || hasAVX(); }
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bool hasXMMInt() const { return hasSSE2() || hasAVX(); }
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bool hasSSE3orAVX() const { return hasSSE3() || hasAVX(); }
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bool hasSSSE3orAVX() const { return hasSSSE3() || hasAVX(); }
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bool hasSSE41orAVX() const { return hasSSE41() || hasAVX(); }
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bool hasSSE42orAVX() const { return hasSSE42() || hasAVX(); }
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bool hasAES() const { return HasAES; }
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bool hasCLMUL() const { return HasCLMUL; }
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bool hasFMA3() const { return HasFMA3; }
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