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Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105060 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -605,11 +605,29 @@ unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
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}
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}
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Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
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Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
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for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
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unsigned NumVals = N->getNumValues();
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if (!NumVals)
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return Sched::RegPressure;
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for (unsigned i = 0; i != NumVals; ++i) {
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EVT VT = N->getValueType(i);
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EVT VT = N->getValueType(i);
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if (VT.isFloatingPoint() || VT.isVector())
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if (VT.isFloatingPoint() || VT.isVector())
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return Sched::Latency;
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return Sched::Latency;
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}
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}
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if (!N->isMachineOpcode())
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return Sched::RegPressure;
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// Load are scheduled for latency even if there instruction itinerary
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// is not available.
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
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if (TID.mayLoad())
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return Sched::Latency;
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const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData();
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if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2)
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return Sched::Latency;
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return Sched::RegPressure;
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return Sched::RegPressure;
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}
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}
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