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Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.

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Invalid operation is signaled if the operand of these instructions is NaN.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154545 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-04-11 22:49:04 +00:00
parent b318cc16c9
commit c12a6e6b53
4 changed files with 117 additions and 0 deletions
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63
lib/Target/Mips/MipsISelLowering.cpp
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@ -147,6 +147,11 @@ MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
if (!TM.Options.NoNaNsFPMath) {
setOperationAction(ISD::FABS, MVT::f32, Custom);
setOperationAction(ISD::FABS, MVT::f64, Custom);
}
if (HasMips64) {
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
@ -734,6 +739,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
case ISD::SETCC: return LowerSETCC(Op, DAG);
case ISD::VASTART: return LowerVASTART(Op, DAG);
case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
case ISD::FABS: return LowerFABS(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
@ -1857,6 +1863,63 @@ MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
}
static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
DebugLoc DL = Op.getDebugLoc();
// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
// to i32.
SDValue X = (Op.getValueType() == MVT::f32) ?
DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
Const1);
// Clear MSB.
if (HasR2)
Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
DAG.getRegister(Mips::ZERO, MVT::i32),
DAG.getConstant(31, MVT::i32), Const1, X);
else {
SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
}
if (Op.getValueType() == MVT::f32)
return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Op.getOperand(0), DAG.getConstant(0, MVT::i32));
return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
}
static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
DebugLoc DL = Op.getDebugLoc();
// Bitcast to integer node.
SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
// Clear MSB.
if (HasR2)
Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
DAG.getRegister(Mips::ZERO_64, MVT::i64),
DAG.getConstant(63, MVT::i32), Const1, X);
else {
SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
}
return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
}
SDValue
MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
}
SDValue MipsTargetLowering::
LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
// check the depth

1
lib/Target/Mips/MipsISelLowering.h
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@ -131,6 +131,7 @@ namespace llvm {
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;

1
lib/Target/Mips/MipsInstrFPU.td
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@ -190,6 +190,7 @@ let Predicates = [IsFP64bit] in {
def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
}
let Predicates = [NoNaNsFPMath] in
defm FABS : FFR1P_M<0x5, "abs", fabs>;
defm FNEG : FFR1P_M<0x7, "neg", fneg>;
defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;

52
test/CodeGen/Mips/fabs.ll Normal file
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@ -0,0 +1,52 @@
; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=32
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2
; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2
; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefix=NO-NAN
define float @foo0(float %a) nounwind readnone {
entry:
; 32: lui $[[T0:[0-9]+]], 32767
; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; 32: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
; 32: mtc1 $[[AND]], $f0
; 32R2: ins $[[INS:[0-9]+]], $zero, 31, 1
; 32R2: mtc1 $[[INS]], $f0
; NO-NAN: abs.s
%call = tail call float @fabsf(float %a) nounwind readnone
ret float %call
}
declare float @fabsf(float) nounwind readnone
define double @foo1(double %a) nounwind readnone {
entry:
; 32: lui $[[T0:[0-9]+]], 32767
; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; 32: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
; 32: mtc1 $[[AND]], $f1
; 32R2: ins $[[INS:[0-9]+]], $zero, 31, 1
; 32R2: mtc1 $[[INS]], $f1
; 64: daddiu $[[T0:[0-9]+]], $zero, 1
; 64: dsll $[[T1:[0-9]+]], ${{[0-9]+}}, 63
; 64: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1
; 64: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
; 64: dmtc1 $[[AND]], $f0
; 64R2: dins $[[INS:[0-9]+]], $zero, 63, 1
; 64R2: dmtc1 $[[INS]], $f0
; NO-NAN: abs.d
%call = tail call double @fabs(double %a) nounwind readnone
ret double %call
}
declare double @fabs(double) nounwind readnone