From c149fbbe279ef623e6067304fd08dc1a62d74f7d Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Tue, 20 Aug 2013 08:38:21 +0000 Subject: [PATCH] [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188767 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IR/IntrinsicsMips.td | 21 +++ lib/Target/Mips/MipsMSAInstrFormats.td | 5 + lib/Target/Mips/MipsMSAInstrInfo.td | 59 +++++++++ test/CodeGen/Mips/msa/vec.ll | 176 +++++++++++++++++++++++++ 4 files changed, 261 insertions(+) create mode 100644 test/CodeGen/Mips/msa/vec.ll diff --git a/include/llvm/IR/IntrinsicsMips.td b/include/llvm/IR/IntrinsicsMips.td index 0c413dcdb1f..9e6d202d7a3 100644 --- a/include/llvm/IR/IntrinsicsMips.td +++ b/include/llvm/IR/IntrinsicsMips.td @@ -447,6 +447,9 @@ def int_mips_addvi_w : GCCBuiltin<"__builtin_msa_addvi_w">, def int_mips_addvi_d : GCCBuiltin<"__builtin_msa_addvi_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [Commutative]>; +def int_mips_and_v : GCCBuiltin<"__builtin_msa_and_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_andi_b : GCCBuiltin<"__builtin_msa_andi_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; @@ -558,9 +561,15 @@ def int_mips_binsri_w : GCCBuiltin<"__builtin_msa_binsri_w">, def int_mips_binsri_d : GCCBuiltin<"__builtin_msa_binsri_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], []>; +def int_mips_bmnz_v : GCCBuiltin<"__builtin_msa_bmnz_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_bmnzi_b : GCCBuiltin<"__builtin_msa_bmnzi_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; +def int_mips_bmz_v : GCCBuiltin<"__builtin_msa_bmz_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_bmzi_b : GCCBuiltin<"__builtin_msa_bmzi_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; @@ -582,6 +591,9 @@ def int_mips_bnegi_w : GCCBuiltin<"__builtin_msa_bnegi_w">, def int_mips_bnegi_d : GCCBuiltin<"__builtin_msa_bnegi_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], []>; +def int_mips_bsel_v : GCCBuiltin<"__builtin_msa_bsel_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_bseli_b : GCCBuiltin<"__builtin_msa_bseli_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; def int_mips_bseli_h : GCCBuiltin<"__builtin_msa_bseli_h">, @@ -1219,9 +1231,15 @@ def int_mips_nlzc_w : GCCBuiltin<"__builtin_msa_nlzc_w">, def int_mips_nlzc_d : GCCBuiltin<"__builtin_msa_nlzc_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty], []>; +def int_mips_nor_v : GCCBuiltin<"__builtin_msa_nor_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_nori_b : GCCBuiltin<"__builtin_msa_nori_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; +def int_mips_or_v : GCCBuiltin<"__builtin_msa_or_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_ori_b : GCCBuiltin<"__builtin_msa_ori_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; @@ -1430,6 +1448,9 @@ def int_mips_vshf_w : GCCBuiltin<"__builtin_msa_vshf_w">, def int_mips_vshf_d : GCCBuiltin<"__builtin_msa_vshf_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [Commutative]>; +def int_mips_xor_v : GCCBuiltin<"__builtin_msa_xor_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_xori_b : GCCBuiltin<"__builtin_msa_xori_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; } diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td index 6f1e58f2c69..35082c2912f 100644 --- a/lib/Target/Mips/MipsMSAInstrFormats.td +++ b/lib/Target/Mips/MipsMSAInstrFormats.td @@ -109,3 +109,8 @@ class MSA_I10_FMT major, bits<2> df, bits<6> minor>: MSAInst { let Inst{22-21} = df; let Inst{5-0} = minor; } + +class MSA_VEC_FMT major, bits<6> minor>: MSAInst { + let Inst{25-21} = major; + let Inst{5-0} = minor; +} diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index c03924fbd15..1657962472e 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -65,6 +65,8 @@ class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>; class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>; class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>; +class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>; + class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>; class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>; @@ -127,8 +129,12 @@ class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>; class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>; class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>; +class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>; + class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>; +class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>; + class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>; class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>; @@ -141,6 +147,8 @@ class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>; class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>; class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>; +class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>; + class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>; class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>; @@ -508,8 +516,12 @@ class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>; class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>; class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>; +class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>; + class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>; +class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>; + class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>; class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>; @@ -631,6 +643,8 @@ class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>; class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>; class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>; +class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>; + class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>; // Instruction desc. @@ -784,6 +798,16 @@ class MSA_INSERT_DESC_BASE { + dag OutOperandList = (outs RCWD:$wd); + dag InOperandList = (ins RCWS:$ws, RCWT:$wt); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); + list Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, RCWT:$wt))]; + InstrItinClass Itinerary = itin; +} + class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, NoItinerary, MSA128, MSA128>, IsCommutable; class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, NoItinerary, @@ -850,6 +874,9 @@ class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", int_mips_addvi_w, NoItinerary, class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", int_mips_addvi_d, NoItinerary, MSA128, MSA128>; +class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", int_mips_and_v, NoItinerary, + MSA128, MSA128>; + class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", int_mips_andi_b, NoItinerary, MSA128, MSA128>; @@ -969,9 +996,15 @@ class BINSRI_W_DESC : MSA_BIT_W_DESC_BASE<"binsri.w", int_mips_binsri_w, class BINSRI_D_DESC : MSA_BIT_D_DESC_BASE<"binsri.d", int_mips_binsri_d, NoItinerary, MSA128, MSA128>; +class BMNZ_V_DESC : MSA_VEC_DESC_BASE<"bmnz.v", int_mips_bmnz_v, NoItinerary, + MSA128, MSA128>; + class BMNZI_B_DESC : MSA_I8_DESC_BASE<"bmnzi.b", int_mips_bmnzi_b, NoItinerary, MSA128, MSA128>; +class BMZ_V_DESC : MSA_VEC_DESC_BASE<"bmz.v", int_mips_bmz_v, NoItinerary, + MSA128, MSA128>; + class BMZI_B_DESC : MSA_I8_DESC_BASE<"bmzi.b", int_mips_bmzi_b, NoItinerary, MSA128, MSA128>; @@ -993,6 +1026,9 @@ class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", int_mips_bnegi_w, class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", int_mips_bnegi_d, NoItinerary, MSA128, MSA128>; +class BSEL_V_DESC : MSA_VEC_DESC_BASE<"bsel.v", int_mips_bsel_v, NoItinerary, + MSA128, MSA128>; + class BSELI_B_DESC : MSA_I8_DESC_BASE<"bseli.b", int_mips_bseli_b, NoItinerary, MSA128, MSA128>; @@ -1661,9 +1697,15 @@ class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", int_mips_nlzc_w, class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", int_mips_nlzc_d, NoItinerary, MSA128, MSA128>; +class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", int_mips_nor_v, NoItinerary, + MSA128, MSA128>; + class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", int_mips_nori_b, NoItinerary, MSA128, MSA128>; +class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", int_mips_or_v, NoItinerary, + MSA128, MSA128>; + class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", int_mips_ori_b, NoItinerary, MSA128, MSA128>; @@ -1888,6 +1930,9 @@ class VSHF_W_DESC : MSA_3R_DESC_BASE<"vshf.w", int_mips_vshf_w, class VSHF_D_DESC : MSA_3R_DESC_BASE<"vshf.d", int_mips_vshf_d, NoItinerary, MSA128, MSA128>; +class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", int_mips_xor_v, NoItinerary, + MSA128, MSA128>; + class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", int_mips_xori_b, NoItinerary, MSA128, MSA128>; // Instruction defs. @@ -1921,6 +1966,8 @@ def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC, Requires<[HasMSA]>; def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC, Requires<[HasMSA]>; def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC, Requires<[HasMSA]>; +def AND_V : AND_V_ENC, AND_V_DESC, Requires<[HasMSA]>; + def ANDI_B : ANDI_B_ENC, ANDI_B_DESC, Requires<[HasMSA]>; def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC, Requires<[HasMSA]>; @@ -1983,8 +2030,12 @@ def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC, Requires<[HasMSA]>; def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC, Requires<[HasMSA]>; def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC, Requires<[HasMSA]>; +def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC, Requires<[HasMSA]>; + def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC, Requires<[HasMSA]>; +def BMZ_V : BMZ_V_ENC, BMZ_V_DESC, Requires<[HasMSA]>; + def BMZI_B : BMZI_B_ENC, BMZI_B_DESC, Requires<[HasMSA]>; def BNEG_B : BNEG_B_ENC, BNEG_B_DESC, Requires<[HasMSA]>; @@ -1997,6 +2048,8 @@ def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC, Requires<[HasMSA]>; def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC, Requires<[HasMSA]>; def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC, Requires<[HasMSA]>; +def BSEL_V : BSEL_V_ENC, BSEL_V_DESC, Requires<[HasMSA]>; + def BSELI_B : BSELI_B_ENC, BSELI_B_DESC, Requires<[HasMSA]>; def BSET_B : BSET_B_ENC, BSET_B_DESC, Requires<[HasMSA]>; @@ -2363,8 +2416,12 @@ def NLZC_H : NLZC_H_ENC, NLZC_H_DESC, Requires<[HasMSA]>; def NLZC_W : NLZC_W_ENC, NLZC_W_DESC, Requires<[HasMSA]>; def NLZC_D : NLZC_D_ENC, NLZC_D_DESC, Requires<[HasMSA]>; +def NOR_V : NOR_V_ENC, NOR_V_DESC, Requires<[HasMSA]>; + def NORI_B : NORI_B_ENC, NORI_B_DESC, Requires<[HasMSA]>; +def OR_V : OR_V_ENC, OR_V_DESC, Requires<[HasMSA]>; + def ORI_B : ORI_B_ENC, ORI_B_DESC, Requires<[HasMSA]>; def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC, Requires<[HasMSA]>; @@ -2486,6 +2543,8 @@ def VSHF_H : VSHF_H_ENC, VSHF_H_DESC, Requires<[HasMSA]>; def VSHF_W : VSHF_W_ENC, VSHF_W_DESC, Requires<[HasMSA]>; def VSHF_D : VSHF_D_ENC, VSHF_D_DESC, Requires<[HasMSA]>; +def XOR_V : XOR_V_ENC, XOR_V_DESC, Requires<[HasMSA]>; + def XORI_B : XORI_B_ENC, XORI_B_DESC, Requires<[HasMSA]>; // Patterns. diff --git a/test/CodeGen/Mips/msa/vec.ll b/test/CodeGen/Mips/msa/vec.ll new file mode 100644 index 00000000000..8a9d3896872 --- /dev/null +++ b/test/CodeGen/Mips/msa/vec.ll @@ -0,0 +1,176 @@ +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s +; +; Test the MSA intrinsics that are encoded with the VEC instruction format. + +@llvm_mips_and_v_b_ARG1 = global <16 x i8> , align 16 +@llvm_mips_and_v_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_and_v_b_RES = global <16 x i8> , align 16 + +define void @llvm_mips_and_v_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_and_v_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_and_v_b_ARG2 + %2 = bitcast <16 x i8> %0 to <16 x i8> + %3 = bitcast <16 x i8> %1 to <16 x i8> + %4 = tail call <16 x i8> @llvm.mips.and.v(<16 x i8> %2, <16 x i8> %3) + %5 = bitcast <16 x i8> %4 to <16 x i8> + store <16 x i8> %5, <16 x i8>* @llvm_mips_and_v_b_RES + ret void +} + +; CHECK: llvm_mips_and_v_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: and.v +; CHECK: st.b +; CHECK: .size llvm_mips_and_v_b_test +; +@llvm_mips_bmnz_v_b_ARG1 = global <16 x i8> , align 16 +@llvm_mips_bmnz_v_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_bmnz_v_b_RES = global <16 x i8> , align 16 + +define void @llvm_mips_bmnz_v_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_bmnz_v_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_bmnz_v_b_ARG2 + %2 = bitcast <16 x i8> %0 to <16 x i8> + %3 = bitcast <16 x i8> %1 to <16 x i8> + %4 = tail call <16 x i8> @llvm.mips.bmnz.v(<16 x i8> %2, <16 x i8> %3) + %5 = bitcast <16 x i8> %4 to <16 x i8> + store <16 x i8> %5, <16 x i8>* @llvm_mips_bmnz_v_b_RES + ret void +} + +; CHECK: llvm_mips_bmnz_v_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: bmnz.v +; CHECK: st.b +; CHECK: .size llvm_mips_bmnz_v_b_test +; +@llvm_mips_bmz_v_b_ARG1 = global <16 x i8> , align 16 +@llvm_mips_bmz_v_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_bmz_v_b_RES = global <16 x i8> , align 16 + +define void @llvm_mips_bmz_v_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_bmz_v_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_bmz_v_b_ARG2 + %2 = bitcast <16 x i8> %0 to <16 x i8> + %3 = bitcast <16 x i8> %1 to <16 x i8> + %4 = tail call <16 x i8> @llvm.mips.bmz.v(<16 x i8> %2, <16 x i8> %3) + %5 = bitcast <16 x i8> %4 to <16 x i8> + store <16 x i8> %5, <16 x i8>* @llvm_mips_bmz_v_b_RES + ret void +} + +; CHECK: llvm_mips_bmz_v_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: bmz.v +; CHECK: st.b +; CHECK: .size llvm_mips_bmz_v_b_test +; +@llvm_mips_bmz_v_h_ARG1 = global <8 x i16> , align 16 +@llvm_mips_bmz_v_h_ARG2 = global <8 x i16> , align 16 +@llvm_mips_bmz_v_h_RES = global <8 x i16> , align 16 + +@llvm_mips_bsel_v_b_ARG1 = global <16 x i8> , align 16 +@llvm_mips_bsel_v_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_bsel_v_b_RES = global <16 x i8> , align 16 + +define void @llvm_mips_bsel_v_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_bsel_v_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_bsel_v_b_ARG2 + %2 = bitcast <16 x i8> %0 to <16 x i8> + %3 = bitcast <16 x i8> %1 to <16 x i8> + %4 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %2, <16 x i8> %3) + %5 = bitcast <16 x i8> %4 to <16 x i8> + store <16 x i8> %5, <16 x i8>* @llvm_mips_bsel_v_b_RES + ret void +} + +; CHECK: llvm_mips_bsel_v_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: bsel.v +; CHECK: st.b +; CHECK: .size llvm_mips_bsel_v_b_test +; +@llvm_mips_nor_v_b_ARG1 = global <16 x i8> , align 16 +@llvm_mips_nor_v_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_nor_v_b_RES = global <16 x i8> , align 16 + +define void @llvm_mips_nor_v_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_nor_v_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_nor_v_b_ARG2 + %2 = bitcast <16 x i8> %0 to <16 x i8> + %3 = bitcast <16 x i8> %1 to <16 x i8> + %4 = tail call <16 x i8> @llvm.mips.nor.v(<16 x i8> %2, <16 x i8> %3) + %5 = bitcast <16 x i8> %4 to <16 x i8> + store <16 x i8> %5, <16 x i8>* @llvm_mips_nor_v_b_RES + ret void +} + +; CHECK: llvm_mips_nor_v_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: nor.v +; CHECK: st.b +; CHECK: .size llvm_mips_nor_v_b_test +; +@llvm_mips_or_v_b_ARG1 = global <16 x i8> , align 16 +@llvm_mips_or_v_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_or_v_b_RES = global <16 x i8> , align 16 + +define void @llvm_mips_or_v_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_or_v_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_or_v_b_ARG2 + %2 = bitcast <16 x i8> %0 to <16 x i8> + %3 = bitcast <16 x i8> %1 to <16 x i8> + %4 = tail call <16 x i8> @llvm.mips.or.v(<16 x i8> %2, <16 x i8> %3) + %5 = bitcast <16 x i8> %4 to <16 x i8> + store <16 x i8> %5, <16 x i8>* @llvm_mips_or_v_b_RES + ret void +} + +; CHECK: llvm_mips_or_v_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: or.v +; CHECK: st.b +; CHECK: .size llvm_mips_or_v_b_test +; +@llvm_mips_xor_v_b_ARG1 = global <16 x i8> , align 16 +@llvm_mips_xor_v_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_xor_v_b_RES = global <16 x i8> , align 16 + +define void @llvm_mips_xor_v_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_xor_v_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_xor_v_b_ARG2 + %2 = bitcast <16 x i8> %0 to <16 x i8> + %3 = bitcast <16 x i8> %1 to <16 x i8> + %4 = tail call <16 x i8> @llvm.mips.xor.v(<16 x i8> %2, <16 x i8> %3) + %5 = bitcast <16 x i8> %4 to <16 x i8> + store <16 x i8> %5, <16 x i8>* @llvm_mips_xor_v_b_RES + ret void +} + +; CHECK: llvm_mips_xor_v_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: xor.v +; CHECK: st.b +; CHECK: .size llvm_mips_xor_v_b_test +; +declare <16 x i8> @llvm.mips.and.v(<16 x i8>, <16 x i8>) nounwind +declare <16 x i8> @llvm.mips.bmnz.v(<16 x i8>, <16 x i8>) nounwind +declare <16 x i8> @llvm.mips.bmz.v(<16 x i8>, <16 x i8>) nounwind +declare <16 x i8> @llvm.mips.bsel.v(<16 x i8>, <16 x i8>) nounwind +declare <16 x i8> @llvm.mips.nor.v(<16 x i8>, <16 x i8>) nounwind +declare <16 x i8> @llvm.mips.or.v(<16 x i8>, <16 x i8>) nounwind +declare <16 x i8> @llvm.mips.xor.v(<16 x i8>, <16 x i8>) nounwind