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Add more analysis of the sign bit of an srem instruction. If the LHS is negative

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then the result could go either way. If it's provably positive then so is the
srem. Fixes PR9343 #7!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127146 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nick Lewycky
2011-03-07 01:50:10 +00:00
parent 128ccbb8e5
commit c14bc77315
3 changed files with 44 additions and 0 deletions
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12
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
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@@ -712,6 +712,18 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
}
}
// The sign bit is the LHS's sign bit, except when the result of the
// remainder is zero.
if (DemandedMask.isNegative() && KnownZero.isNonNegative()) {
APInt Mask2 = APInt::getSignBit(BitWidth);
APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
ComputeMaskedBits(I->getOperand(0), Mask2, LHSKnownZero, LHSKnownOne,
Depth+1);
// If it's known zero, our sign bit is also zero.
if (LHSKnownZero.isNegative())
KnownZero |= LHSKnownZero;
}
break;
case Instruction::URem: {
APInt KnownZero2(BitWidth, 0), KnownOne2(BitWidth, 0);