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synced 2024-08-21 03:29:40 +00:00
x86 users can now return arbitrary sized structs. Structs too large to fit in return registers will be returned through a hidden sret parameter introduced during SelectionDAG construction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86876 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -951,13 +951,13 @@ SDValue SelectionDAGLowering::getValue(const Value *V) {
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/// Get the EVTs and ArgFlags collections that represent the return type
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/// of the given function. This does not require a DAG or a return value, and
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/// is suitable for use before any DAGs for the function are constructed.
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static void getReturnInfo(const Function* F, SmallVectorImpl<EVT> &OutVTs,
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static void getReturnInfo(const Type* ReturnType,
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Attributes attr, SmallVectorImpl<EVT> &OutVTs,
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SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags,
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TargetLowering &TLI) {
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const Type* ReturnType = F->getReturnType();
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TargetLowering &TLI,
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SmallVectorImpl<uint64_t> *Offsets = 0) {
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(TLI, ReturnType, ValueVTs);
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ComputeValueVTs(TLI, ReturnType, ValueVTs, Offsets);
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unsigned NumValues = ValueVTs.size();
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if ( NumValues == 0 ) return;
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@ -965,9 +965,9 @@ static void getReturnInfo(const Function* F, SmallVectorImpl<EVT> &OutVTs,
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EVT VT = ValueVTs[j];
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
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if (F->paramHasAttr(0, Attribute::SExt))
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if (attr & Attribute::SExt)
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ExtendKind = ISD::SIGN_EXTEND;
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else if (F->paramHasAttr(0, Attribute::ZExt))
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else if (attr & Attribute::ZExt)
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ExtendKind = ISD::ZERO_EXTEND;
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// FIXME: C calling convention requires the return type to be promoted to
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@ -975,26 +975,25 @@ static void getReturnInfo(const Function* F, SmallVectorImpl<EVT> &OutVTs,
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// conventions. The frontend should mark functions whose return values
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// require promoting with signext or zeroext attributes.
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if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
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EVT MinVT = TLI.getRegisterType(F->getContext(), MVT::i32);
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EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
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if (VT.bitsLT(MinVT))
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VT = MinVT;
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}
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unsigned NumParts = TLI.getNumRegisters(F->getContext(), VT);
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EVT PartVT = TLI.getRegisterType(F->getContext(), VT);
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unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
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EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
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// 'inreg' on function refers to return value
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ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
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if (F->paramHasAttr(0, Attribute::InReg))
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if (attr & Attribute::InReg)
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Flags.setInReg();
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// Propagate extension type if any
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if (F->paramHasAttr(0, Attribute::SExt))
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if (attr & Attribute::SExt)
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Flags.setSExt();
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else if (F->paramHasAttr(0, Attribute::ZExt))
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else if (attr & Attribute::ZExt)
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Flags.setZExt();
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for (unsigned i = 0; i < NumParts; ++i)
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{
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for (unsigned i = 0; i < NumParts; ++i) {
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OutVTs.push_back(PartVT);
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OutFlags.push_back(Flags);
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}
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@ -1004,6 +1003,39 @@ static void getReturnInfo(const Function* F, SmallVectorImpl<EVT> &OutVTs,
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void SelectionDAGLowering::visitRet(ReturnInst &I) {
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SDValue Chain = getControlRoot();
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SmallVector<ISD::OutputArg, 8> Outs;
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FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
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if (!FLI.CanLowerReturn) {
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unsigned DemoteReg = FLI.DemoteRegister;
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const Function *F = I.getParent()->getParent();
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// Emit a store of the return value through the virtual register.
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// Leave Outs empty so that LowerReturn won't try to load return
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// registers the usual way.
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SmallVector<EVT, 1> PtrValueVTs;
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ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
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PtrValueVTs);
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SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
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SDValue RetOp = getValue(I.getOperand(0));
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SmallVector<EVT, 4> ValueVTs;
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SmallVector<uint64_t, 4> Offsets;
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ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
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unsigned NumValues = ValueVTs.size();
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SmallVector<SDValue, 4> Chains(NumValues);
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EVT PtrVT = PtrValueVTs[0];
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for (unsigned i = 0; i != NumValues; ++i)
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Chains[i] = DAG.getStore(Chain, getCurDebugLoc(),
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SDValue(RetOp.getNode(), RetOp.getResNo() + i),
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DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, RetPtr,
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DAG.getConstant(Offsets[i], PtrVT)),
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NULL, Offsets[i], false, 0);
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Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
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MVT::Other, &Chains[0], NumValues);
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}
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else {
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for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
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@ -1054,6 +1086,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
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Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
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}
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}
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}
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bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
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CallingConv::ID CallConv =
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@ -4453,15 +4486,52 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
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MachineBasicBlock *LandingPad) {
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const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
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const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
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const Type *RetTy = FTy->getReturnType();
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MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
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unsigned BeginLabel = 0, EndLabel = 0;
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TargetLowering::ArgListTy Args;
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TargetLowering::ArgListEntry Entry;
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Args.reserve(CS.arg_size());
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unsigned j = 1;
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// Check whether the function can return without sret-demotion.
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SmallVector<EVT, 4> OutVTs;
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SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
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SmallVector<uint64_t, 4> Offsets;
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getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
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OutVTs, OutsFlags, TLI, &Offsets);
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bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
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FTy->isVarArg(), OutVTs, OutsFlags, DAG);
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SDValue DemoteStackSlot;
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if (!CanLowerReturn) {
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uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
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FTy->getReturnType());
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unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
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FTy->getReturnType());
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MachineFunction &MF = DAG.getMachineFunction();
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int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
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const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
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DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
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Entry.Node = DemoteStackSlot;
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Entry.Ty = StackSlotPtrType;
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Entry.isSExt = false;
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Entry.isZExt = false;
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Entry.isInReg = false;
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Entry.isSRet = true;
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Entry.isNest = false;
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Entry.isByVal = false;
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Entry.Alignment = Align;
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Args.push_back(Entry);
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RetTy = Type::getVoidTy(FTy->getContext());
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}
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for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
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i != e; ++i, ++j) {
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i != e; ++i) {
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SDValue ArgNode = getValue(*i);
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Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
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@ -4497,7 +4567,7 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
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isTailCall = false;
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std::pair<SDValue,SDValue> Result =
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TLI.LowerCallTo(getRoot(), CS.getType(),
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TLI.LowerCallTo(getRoot(), RetTy,
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CS.paramHasAttr(0, Attribute::SExt),
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CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
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CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
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@ -4511,6 +4581,35 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
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"Null value expected with tail call!");
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if (Result.first.getNode())
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setValue(CS.getInstruction(), Result.first);
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else if (!CanLowerReturn && Result.second.getNode()) {
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// The instruction result is the result of loading from the
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// hidden sret parameter.
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SmallVector<EVT, 1> PVTs;
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const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
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ComputeValueVTs(TLI, PtrRetTy, PVTs);
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assert(PVTs.size() == 1 && "Pointers should fit in one register");
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EVT PtrVT = PVTs[0];
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unsigned NumValues = OutVTs.size();
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SmallVector<SDValue, 4> Values(NumValues);
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SmallVector<SDValue, 4> Chains(NumValues);
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for (unsigned i = 0; i < NumValues; ++i) {
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SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second,
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DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, DemoteStackSlot,
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DAG.getConstant(Offsets[i], PtrVT)),
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NULL, Offsets[i], false, 1);
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Values[i] = L;
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Chains[i] = L.getValue(1);
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}
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SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
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MVT::Other, &Chains[0], NumValues);
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PendingLoads.push_back(Chain);
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setValue(CS.getInstruction(), DAG.getNode(ISD::MERGE_VALUES,
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getCurDebugLoc(), DAG.getVTList(&OutVTs[0], NumValues),
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&Values[0], NumValues));
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}
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// As a special case, a null chain means that a tail call has
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// been emitted and the DAG root is already updated.
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if (Result.second.getNode())
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@ -5779,17 +5878,32 @@ void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
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SDValue OldRoot = DAG.getRoot();
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DebugLoc dl = SDL->getCurDebugLoc();
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const TargetData *TD = TLI.getTargetData();
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SmallVector<ISD::InputArg, 16> Ins;
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// Check whether the function can return without sret-demotion.
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SmallVector<EVT, 4> OutVTs;
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SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
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getReturnInfo(&F, OutVTs, OutsFlags, TLI);
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// For now, assert and bail out if it can't.
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assert(TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(), OutVTs, OutsFlags,
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DAG) && "Cannot fit return value in registers!");
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getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
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OutVTs, OutsFlags, TLI);
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FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
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FLI.CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(),
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OutVTs, OutsFlags, DAG);
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if (!FLI.CanLowerReturn) {
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// Put in an sret pointer parameter before all the other parameters.
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SmallVector<EVT, 1> ValueVTs;
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ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
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// NOTE: Assuming that a pointer will never break down to more than one VT
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// or one register.
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ISD::ArgFlagsTy Flags;
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Flags.setSRet();
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EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), ValueVTs[0]);
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ISD::InputArg RetArg(Flags, RegisterVT, true);
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Ins.push_back(RetArg);
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}
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// Set up the incoming argument description vector.
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SmallVector<ISD::InputArg, 16> Ins;
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unsigned Idx = 1;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
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I != E; ++I, ++Idx) {
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@ -5867,6 +5981,28 @@ void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
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// Set up the argument values.
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unsigned i = 0;
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Idx = 1;
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if (!FLI.CanLowerReturn) {
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// Create a virtual register for the sret pointer, and put in a copy
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// from the sret argument into it.
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SmallVector<EVT, 1> ValueVTs;
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ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
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EVT VT = ValueVTs[0];
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EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
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ISD::NodeType AssertOp = ISD::DELETED_NODE;
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SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT,
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VT, AssertOp);
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MachineFunction& MF = SDL->DAG.getMachineFunction();
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MachineRegisterInfo& RegInfo = MF.getRegInfo();
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unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
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FLI.DemoteRegister = SRetReg;
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NewRoot = SDL->DAG.getCopyToReg(NewRoot, SDL->getCurDebugLoc(), SRetReg, ArgValue);
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DAG.setRoot(NewRoot);
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// i indexes lowered arguments. Bump it past the hidden sret argument.
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// Idx indexes LLVM arguments. Don't touch it.
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++i;
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}
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
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++I, ++Idx) {
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SmallVector<SDValue, 4> ArgValues;
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@ -90,6 +90,14 @@ public:
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MachineFunction *MF;
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MachineRegisterInfo *RegInfo;
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/// CanLowerReturn - true iff the function's return value can be lowered to
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/// registers.
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bool CanLowerReturn;
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/// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
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/// allocated to hold a pointer to the hidden sret parameter.
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unsigned DemoteRegister;
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explicit FunctionLoweringInfo(TargetLowering &TLI);
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/// set - Initialize this FunctionLoweringInfo with the given Function
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17
test/CodeGen/X86/bigstructret.ll
Normal file
17
test/CodeGen/X86/bigstructret.ll
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@ -0,0 +1,17 @@
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; RUN: llc < %s -march=x86 -o %t
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; RUN: grep "movl .24601, 12(%ecx)" %t
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; RUN: grep "movl .48, 8(%ecx)" %t
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; RUN: grep "movl .24, 4(%ecx)" %t
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; RUN: grep "movl .12, (%ecx)" %t
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%0 = type { i32, i32, i32, i32 }
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define internal fastcc %0 @ReturnBigStruct() nounwind readnone {
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entry:
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%0 = insertvalue %0 zeroinitializer, i32 12, 0
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%1 = insertvalue %0 %0, i32 24, 1
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%2 = insertvalue %0 %1, i32 48, 2
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%3 = insertvalue %0 %2, i32 24601, 3
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ret %0 %3
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}
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