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https://github.com/c64scene-ar/llvm-6502.git
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Add jump tables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75984 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -187,6 +187,9 @@ bool SystemZAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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if (TAI->hasDotTypeDotSizeDirective())
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O << "\t.size\t" << CurrentFnName << ", .-" << CurrentFnName << '\n';
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// Print out jump tables referenced by the function.
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EmitJumpTableInfo(MF.getJumpTableInfo(), MF);
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O.flush();
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// We didn't modify anything
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@ -228,6 +231,11 @@ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
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return;
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case MachineOperand::MO_MachineBasicBlock:
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printBasicBlockLabel(MO.getMBB());
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return;
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case MachineOperand::MO_JumpTableIndex:
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O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_'
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<< MO.getIndex();
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return;
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case MachineOperand::MO_GlobalAddress: {
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const GlobalValue *GV = MO.getGlobal();
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@ -67,6 +67,7 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::i64, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::JumpTable, MVT::i64, Custom);
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// FIXME: Can we lower these 2 efficiently?
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setOperationAction(ISD::SETCC, MVT::i32, Expand);
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@ -90,6 +91,7 @@ SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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case ISD::BR_CC: return LowerBR_CC(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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default:
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assert(0 && "unimplemented operand");
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return SDValue();
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@ -542,6 +544,15 @@ SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
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}
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SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
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SelectionDAG &DAG) {
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DebugLoc dl = Op.getDebugLoc();
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JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
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SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
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return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
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}
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const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
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@ -70,6 +70,7 @@ namespace llvm {
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCCCArguments(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC);
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@ -96,13 +96,11 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
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}
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let isBranch = 1, isTerminator = 1 in {
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let isBarrier = 1 in
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let isBarrier = 1 in {
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def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
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let isBarrier = 1, isIndirectBranch = 1 in {
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def JMPr : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
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// FIXME: displacement here is 12 bits
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def JMPrri : Pseudo<(outs), (ins rriaddr:$dst), "b\t{$dst}", [(brind rriaddr:$dst)]>;
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let isIndirectBranch = 1 in
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def JMPr : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
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}
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let Uses = [PSW] in {
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@ -699,10 +697,17 @@ def UCMPZX64rm32 : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
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// Non-Instruction Patterns.
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//===----------------------------------------------------------------------===//
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// JumpTable
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def : Pat<(SystemZpcrelwrapper tjumptable:$src), (LA64rm tjumptable:$src)>;
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// anyext
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def : Pat<(i64 (anyext GR32:$src)),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
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// calls
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def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>;
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def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>;
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//===----------------------------------------------------------------------===//
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// Peepholes.
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//===----------------------------------------------------------------------===//
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@ -728,12 +733,6 @@ def : Pat<(extloadi64i8 rriaddr:$src), (MOVZX64rm8 rriaddr:$src)>;
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def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
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def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
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// calls
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def : Pat<(SystemZcall (i64 tglobaladdr:$dst)),
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(CALLi tglobaladdr:$dst)>;
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def : Pat<(SystemZcall (i64 texternalsym:$dst)),
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(CALLi texternalsym:$dst)>;
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// muls
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def : Pat<(mulhs GR32:$src1, GR32:$src2),
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(EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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39
test/CodeGen/SystemZ/09-Switches.ll
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39
test/CodeGen/SystemZ/09-Switches.ll
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@ -0,0 +1,39 @@
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; RUN: llvm-as < %s | llc -march=systemz | grep larl
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define i32 @main(i32 %tmp158) {
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entry:
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switch i32 %tmp158, label %bb336 [
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i32 -2147483648, label %bb338
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i32 -2147483647, label %bb338
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i32 -2147483646, label %bb338
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i32 120, label %bb338
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i32 121, label %bb339
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i32 122, label %bb340
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i32 123, label %bb341
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i32 124, label %bb342
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i32 125, label %bb343
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i32 126, label %bb336
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i32 1024, label %bb338
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i32 0, label %bb338
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i32 1, label %bb338
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i32 2, label %bb338
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i32 3, label %bb338
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i32 4, label %bb338
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i32 5, label %bb338
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]
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bb336:
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ret i32 10
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bb338:
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ret i32 11
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bb339:
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ret i32 12
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bb340:
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ret i32 13
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bb341:
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ret i32 14
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bb342:
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ret i32 15
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bb343:
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ret i32 18
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}
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