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misched interface: Expose the MachineScheduler pass.
Allow targets to provide their own schedulers (subclass of ScheduleDAGInstrs) to the misched pass. Select schedulers using -misched=... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152278 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
parent
fd03ccdded
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c174eaf948
86
include/llvm/CodeGen/MachineScheduler.h
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86
include/llvm/CodeGen/MachineScheduler.h
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@ -0,0 +1,86 @@
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//==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides a MachineSchedRegistry for registering alternative machine
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// schedulers. A Target may provide an alternative scheduler implementation by
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// implementing the following boilerplate:
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//
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// static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext *C) {
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// return new CustomMachineScheduler(C);
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// }
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// static MachineSchedRegistry
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// SchedDefaultRegistry("custom", "Run my target's custom scheduler",
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// createCustomMachineSched);
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//
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//===----------------------------------------------------------------------===//
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#ifndef MACHINESCHEDULER_H
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#define MACHINESCHEDULER_H
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#include "llvm/CodeGen/MachinePassRegistry.h"
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namespace llvm {
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class AliasAnalysis;
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class LiveIntervals;
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class MachineDominatorTree;
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class MachineLoopInfo;
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class ScheduleDAGInstrs;
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/// MachineSchedContext provides enough context from the MachineScheduler pass
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/// for the target to instantiate a scheduler.
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struct MachineSchedContext {
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MachineFunction *MF;
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const MachineLoopInfo *MLI;
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const MachineDominatorTree *MDT;
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AliasAnalysis *AA;
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LiveIntervals *LIS;
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MachineSchedContext(): MF(0), MLI(0), MDT(0), AA(0), LIS(0) {}
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};
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/// MachineSchedRegistry provides a selection of available machine instruction
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/// schedulers.
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class MachineSchedRegistry : public MachinePassRegistryNode {
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public:
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typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *);
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// RegisterPassParser requires a (misnamed) FunctionPassCtor type.
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typedef ScheduleDAGCtor FunctionPassCtor;
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static MachinePassRegistry Registry;
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MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
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: MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
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Registry.Add(this);
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}
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~MachineSchedRegistry() { Registry.Remove(this); }
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// Accessors.
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//
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MachineSchedRegistry *getNext() const {
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return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
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}
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static MachineSchedRegistry *getList() {
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return (MachineSchedRegistry *)Registry.getList();
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}
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static ScheduleDAGCtor getDefault() {
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return (ScheduleDAGCtor)Registry.getDefault();
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}
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static void setDefault(ScheduleDAGCtor C) {
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Registry.setDefault((MachinePassCtor)C);
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}
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static void setListener(MachinePassRegistryListener *L) {
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Registry.setListener(L);
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}
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};
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} // namespace llvm
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#endif
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@ -15,7 +15,7 @@
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#define DEBUG_TYPE "misched"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachinePassRegistry.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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@ -43,14 +43,9 @@ static bool ViewMISchedDAGs = false;
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namespace {
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/// MachineScheduler runs after coalescing and before register allocation.
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class MachineScheduler : public MachineFunctionPass {
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class MachineScheduler : public MachineSchedContext,
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public MachineFunctionPass {
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public:
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MachineFunction *MF;
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const TargetInstrInfo *TII;
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const MachineLoopInfo *MLI;
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const MachineDominatorTree *MDT;
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LiveIntervals *LIS;
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MachineScheduler();
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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@ -78,7 +73,7 @@ INITIALIZE_PASS_END(MachineScheduler, "misched",
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"Machine Instruction Scheduler", false, false)
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MachineScheduler::MachineScheduler()
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: MachineFunctionPass(ID), MF(0), MLI(0), MDT(0) {
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: MachineFunctionPass(ID) {
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initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
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}
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@ -95,47 +90,9 @@ void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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namespace {
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/// MachineSchedRegistry provides a selection of available machine instruction
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/// schedulers.
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class MachineSchedRegistry : public MachinePassRegistryNode {
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public:
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typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineScheduler *);
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// RegisterPassParser requires a (misnamed) FunctionPassCtor type.
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typedef ScheduleDAGCtor FunctionPassCtor;
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static MachinePassRegistry Registry;
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MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
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: MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
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Registry.Add(this);
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}
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~MachineSchedRegistry() { Registry.Remove(this); }
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// Accessors.
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//
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MachineSchedRegistry *getNext() const {
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return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
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}
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static MachineSchedRegistry *getList() {
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return (MachineSchedRegistry *)Registry.getList();
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}
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static ScheduleDAGCtor getDefault() {
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return (ScheduleDAGCtor)Registry.getDefault();
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}
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static void setDefault(ScheduleDAGCtor C) {
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Registry.setDefault((MachinePassCtor)C);
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}
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static void setListener(MachinePassRegistryListener *L) {
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Registry.setListener(L);
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}
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};
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} // namespace
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MachinePassRegistry MachineSchedRegistry::Registry;
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static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P);
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static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedContext *C);
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/// MachineSchedOpt allows command line selection of the scheduler.
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static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
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@ -144,115 +101,15 @@ MachineSchedOpt("misched",
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cl::init(&createDefaultMachineSched), cl::Hidden,
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cl::desc("Machine instruction scheduler to use"));
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//===----------------------------------------------------------------------===//
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// Machine Instruction Scheduling Common Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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/// ScheduleTopDownLive is an implementation of ScheduleDAGInstrs that schedules
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/// machine instructions while updating LiveIntervals.
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class ScheduleTopDownLive : public ScheduleDAGInstrs {
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protected:
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MachineScheduler *Pass;
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public:
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ScheduleTopDownLive(MachineScheduler *P):
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ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false, P->LIS),
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Pass(P) {}
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/// ScheduleDAGInstrs callback.
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void schedule();
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/// Interface implemented by the selected top-down liveinterval scheduler.
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///
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/// Pick the next node to schedule, or return NULL.
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virtual SUnit *pickNode() = 0;
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/// When all preceeding dependencies have been resolved, free this node for
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/// scheduling.
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virtual void releaseNode(SUnit *SU) = 0;
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protected:
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void releaseSucc(SUnit *SU, SDep *SuccEdge);
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void releaseSuccessors(SUnit *SU);
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};
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} // namespace
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/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
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/// NumPredsLeft reaches zero, release the successor node.
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void ScheduleTopDownLive::releaseSucc(SUnit *SU, SDep *SuccEdge) {
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SUnit *SuccSU = SuccEdge->getSUnit();
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#ifndef NDEBUG
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if (SuccSU->NumPredsLeft == 0) {
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dbgs() << "*** Scheduling failed! ***\n";
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SuccSU->dump(this);
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dbgs() << " has been released too many times!\n";
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llvm_unreachable(0);
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}
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#endif
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--SuccSU->NumPredsLeft;
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if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
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releaseNode(SuccSU);
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}
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/// releaseSuccessors - Call releaseSucc on each of SU's successors.
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void ScheduleTopDownLive::releaseSuccessors(SUnit *SU) {
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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releaseSucc(SU, &*I);
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}
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}
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/// schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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void ScheduleTopDownLive::schedule() {
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buildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
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DEBUG(dbgs() << "********** MI Scheduling **********\n");
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(this));
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if (ViewMISchedDAGs) viewGraph();
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// Release any successors of the special Entry node. It is currently unused,
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// but we keep up appearances.
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releaseSuccessors(&EntrySU);
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// Release all DAG roots for scheduling.
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for (std::vector<SUnit>::iterator I = SUnits.begin(), E = SUnits.end();
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I != E; ++I) {
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// A SUnit is ready to schedule if it has no predecessors.
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if (I->Preds.empty())
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releaseNode(&(*I));
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}
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MachineBasicBlock::iterator InsertPos = Begin;
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while (SUnit *SU = pickNode()) {
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DEBUG(dbgs() << "*** Scheduling Instruction:\n"; SU->dump(this));
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// Move the instruction to its new location in the instruction stream.
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MachineInstr *MI = SU->getInstr();
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if (&*InsertPos == MI)
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++InsertPos;
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else {
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BB->splice(InsertPos, BB, MI);
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Pass->LIS->handleMove(MI);
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if (Begin == InsertPos)
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Begin = MI;
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}
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// Release dependent instructions for scheduling.
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releaseSuccessors(SU);
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}
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}
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bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
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// Initialize the context of the pass.
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MF = &mf;
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MLI = &getAnalysis<MachineLoopInfo>();
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MDT = &getAnalysis<MachineDominatorTree>();
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AA = &getAnalysis<AliasAnalysis>();
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LIS = &getAnalysis<LiveIntervals>();
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TII = MF->getTarget().getInstrInfo();
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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
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// Select the scheduler, or set the default.
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MachineSchedRegistry::ScheduleDAGCtor Ctor =
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@ -320,16 +177,118 @@ void MachineScheduler::print(raw_ostream &O, const Module* m) const {
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}
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//===----------------------------------------------------------------------===//
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// Placeholder for extending the machine instruction scheduler.
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// ScheduleTopeDownLive - Base class for basic top-down scheduling with
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// LiveIntervals preservation.
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// ===----------------------------------------------------------------------===//
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namespace {
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/// ScheduleTopDownLive is an implementation of ScheduleDAGInstrs that schedules
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/// machine instructions while updating LiveIntervals.
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class ScheduleTopDownLive : public ScheduleDAGInstrs {
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AliasAnalysis *AA;
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public:
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ScheduleTopDownLive(MachineSchedContext *C):
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ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
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AA(C->AA) {}
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/// ScheduleDAGInstrs interface.
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void schedule();
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/// Interface implemented by the selected top-down liveinterval scheduler.
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///
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/// Pick the next node to schedule, or return NULL.
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virtual SUnit *pickNode() = 0;
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/// When all preceeding dependencies have been resolved, free this node for
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/// scheduling.
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virtual void releaseNode(SUnit *SU) = 0;
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protected:
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void releaseSucc(SUnit *SU, SDep *SuccEdge);
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void releaseSuccessors(SUnit *SU);
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};
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} // namespace
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/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
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/// NumPredsLeft reaches zero, release the successor node.
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void ScheduleTopDownLive::releaseSucc(SUnit *SU, SDep *SuccEdge) {
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SUnit *SuccSU = SuccEdge->getSUnit();
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#ifndef NDEBUG
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if (SuccSU->NumPredsLeft == 0) {
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dbgs() << "*** Scheduling failed! ***\n";
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SuccSU->dump(this);
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dbgs() << " has been released too many times!\n";
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llvm_unreachable(0);
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}
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#endif
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--SuccSU->NumPredsLeft;
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if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
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releaseNode(SuccSU);
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}
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/// releaseSuccessors - Call releaseSucc on each of SU's successors.
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void ScheduleTopDownLive::releaseSuccessors(SUnit *SU) {
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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releaseSucc(SU, &*I);
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}
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}
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/// schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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void ScheduleTopDownLive::schedule() {
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buildSchedGraph(AA);
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DEBUG(dbgs() << "********** MI Scheduling **********\n");
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(this));
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if (ViewMISchedDAGs) viewGraph();
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// Release any successors of the special Entry node. It is currently unused,
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// but we keep up appearances.
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releaseSuccessors(&EntrySU);
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// Release all DAG roots for scheduling.
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for (std::vector<SUnit>::iterator I = SUnits.begin(), E = SUnits.end();
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I != E; ++I) {
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// A SUnit is ready to schedule if it has no predecessors.
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if (I->Preds.empty())
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releaseNode(&(*I));
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}
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MachineBasicBlock::iterator InsertPos = Begin;
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while (SUnit *SU = pickNode()) {
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DEBUG(dbgs() << "*** Scheduling Instruction:\n"; SU->dump(this));
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// Move the instruction to its new location in the instruction stream.
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MachineInstr *MI = SU->getInstr();
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if (&*InsertPos == MI)
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++InsertPos;
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else {
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BB->splice(InsertPos, BB, MI);
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LIS->handleMove(MI);
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if (Begin == InsertPos)
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Begin = MI;
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}
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// Release dependent instructions for scheduling.
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releaseSuccessors(SU);
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}
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}
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//===----------------------------------------------------------------------===//
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// Placeholder for the default machine instruction scheduler.
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//===----------------------------------------------------------------------===//
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namespace {
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class DefaultMachineScheduler : public ScheduleDAGInstrs {
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MachineScheduler *Pass;
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AliasAnalysis *AA;
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public:
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DefaultMachineScheduler(MachineScheduler *P):
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ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false, P->LIS),
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Pass(P) {}
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DefaultMachineScheduler(MachineSchedContext *C):
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ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
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AA(C->AA) {}
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/// schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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@ -337,19 +296,18 @@ public:
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};
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} // namespace
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static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P) {
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return new DefaultMachineScheduler(P);
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static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedContext *C) {
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return new DefaultMachineScheduler(C);
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}
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static MachineSchedRegistry
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SchedDefaultRegistry("default", "Activate the scheduler pass, "
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"but don't reorder instructions",
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createDefaultMachineSched);
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/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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void DefaultMachineScheduler::schedule() {
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buildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
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buildSchedGraph(AA);
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DEBUG(dbgs() << "********** MI Scheduling **********\n");
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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@ -382,8 +340,8 @@ struct ShuffleSUnitOrder {
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class InstructionShuffler : public ScheduleTopDownLive {
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std::priority_queue<SUnit*, std::vector<SUnit*>, ShuffleSUnitOrder> Queue;
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public:
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InstructionShuffler(MachineScheduler *P):
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ScheduleTopDownLive(P) {}
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InstructionShuffler(MachineSchedContext *C):
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ScheduleTopDownLive(C) {}
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/// ScheduleTopDownLive Interface
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@ -400,8 +358,8 @@ public:
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};
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} // namespace
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static ScheduleDAGInstrs *createInstructionShuffler(MachineScheduler *P) {
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return new InstructionShuffler(P);
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static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
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return new InstructionShuffler(C);
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}
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static MachineSchedRegistry ShufflerRegistry("shuffle",
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"Shuffle machine instructions",
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