From c1b46f91f52ea838be6d67708a43ff661810fe6a Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Fri, 17 Jul 2009 00:32:06 +0000 Subject: [PATCH] Fix my brain cramp by inverting the assertion condition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76131 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/VirtRegRewriter.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp index 2213c65f343..abaa8bd212e 100644 --- a/lib/CodeGen/VirtRegRewriter.cpp +++ b/lib/CodeGen/VirtRegRewriter.cpp @@ -491,12 +491,10 @@ static void ReMaterialize(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI, VirtRegMap &VRM) { MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg); -#if 0 #ifndef NDEBUG const TargetInstrDesc &TID = ReMatDefMI->getDesc(); - assert(TID.getNumDefs() != 1 && + assert(TID.getNumDefs() == 1 && "Don't know how to remat instructions that define > 1 values!"); -#endif #endif TII->reMaterialize(MBB, MII, DestReg, ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI);