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https://github.com/c64scene-ar/llvm-6502.git
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Create a new ARM-specific DAG node, VDUP, to represent a splat from a
scalar_to_vector. Generate these VDUP nodes during legalization instead of trying to recognize the pattern during selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78994 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -477,6 +477,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
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case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
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case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
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case ARMISD::VDUP: return "ARMISD::VDUP";
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case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
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case ARMISD::VLD2D: return "ARMISD::VLD2D";
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case ARMISD::VLD3D: return "ARMISD::VLD3D";
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@ -2449,9 +2450,12 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
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// of the same time so that they get CSEd properly.
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if (SVN->isSplat()) {
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int Lane = SVN->getSplatIndex();
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if (Lane != 0)
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return DAG.getNode(ARMISD::VDUPLANE, dl, VT, SVN->getOperand(0),
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DAG.getConstant(Lane, MVT::i32));
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SDValue Op0 = SVN->getOperand(0);
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if (Lane == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
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return DAG.getNode(ARMISD::VDUP, dl, VT, Op0.getOperand(0));
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}
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return DAG.getNode(ARMISD::VDUPLANE, dl, VT, SVN->getOperand(0),
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DAG.getConstant(Lane, MVT::i32));
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}
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if (isVREVMask(SVN, 64))
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return DAG.getNode(ARMISD::VREV64, dl, VT, SVN->getOperand(0));
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@ -115,7 +115,8 @@ namespace llvm {
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VGETLANEu, // zero-extend vector extract element
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VGETLANEs, // sign-extend vector extract element
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// Vector duplicate lane:
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// Vector duplicate:
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VDUP,
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VDUPLANE,
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// Vector load/store with (de)interleaving
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@ -65,6 +65,8 @@ def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
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def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
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def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
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def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
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// VDUPLANE can produce a quad-register result from a double-register source,
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// so the result is not constrained to match the source.
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def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
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@ -1747,20 +1749,14 @@ def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
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// VDUP : Vector Duplicate (from ARM core register to all elements)
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def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
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return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
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}]>;
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class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
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: NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
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NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
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[(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
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[(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
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class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
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: NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
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NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
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[(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
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[(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
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def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
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def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
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@ -1771,16 +1767,12 @@ def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
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def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
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NoItinerary, "vdup", ".32\t$dst, $src",
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[(set DPR:$dst, (v2f32 (splat_lo
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(scalar_to_vector
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(f32 (bitconvert GPR:$src))),
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undef)))]>;
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[(set DPR:$dst, (v2f32 (NEONvdup
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(f32 (bitconvert GPR:$src)))))]>;
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def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
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NoItinerary, "vdup", ".32\t$dst, $src",
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[(set QPR:$dst, (v4f32 (splat_lo
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(scalar_to_vector
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(f32 (bitconvert GPR:$src))),
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undef)))]>;
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[(set QPR:$dst, (v4f32 (NEONvdup
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(f32 (bitconvert GPR:$src)))))]>;
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// VDUP : Vector Duplicate Lane (from scalar to all elements)
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@ -1826,16 +1818,12 @@ def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
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def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
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(outs DPR:$dst), (ins SPR:$src),
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NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
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[(set DPR:$dst, (v2f32 (splat_lo
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(scalar_to_vector SPR:$src),
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undef)))]>;
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[(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
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def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
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(outs QPR:$dst), (ins SPR:$src),
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NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
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[(set QPR:$dst, (v4f32 (splat_lo
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(scalar_to_vector SPR:$src),
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undef)))]>;
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[(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
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// VMOVN : Vector Narrowing Move
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defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
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