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R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208886 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-05-15 14:41:54 +00:00
parent bfffad69b2
commit c1de569ce8
2 changed files with 31 additions and 5 deletions
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11
lib/Target/R600/AMDGPUISelDAGToDAG.cpp
View File

@ -239,12 +239,13 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
AddLoArgs.push_back(SDValue(Lo0, 0));
AddLoArgs.push_back(SDValue(Lo1, 0));
SDNode *AddLo = CurDAG->getMachineNode(AMDGPU::S_ADD_I32, DL,
VTList, AddLoArgs);
SDNode *AddLo = CurDAG->getMachineNode(
isCFDepth0() ? AMDGPU::S_ADD_I32 : AMDGPU::V_ADD_I32_e32,
DL, VTList, AddLoArgs);
SDValue Carry = SDValue(AddLo, 1);
SDNode *AddHi = CurDAG->getMachineNode(AMDGPU::S_ADDC_U32, DL,
MVT::i32, SDValue(Hi0, 0),
SDValue(Hi1, 0), Carry);
SDNode *AddHi = CurDAG->getMachineNode(
isCFDepth0() ? AMDGPU::S_ADDC_U32 : AMDGPU::V_ADDC_U32_e32,
DL, MVT::i32, SDValue(Hi0, 0), SDValue(Hi1, 0), Carry);
SDValue Args[5] = {
CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),

25
test/CodeGen/R600/add.ll
View File

@ -140,3 +140,28 @@ entry:
store i64 %1, i64 addrspace(1)* %out
ret void
}
; Test i64 add inside a branch. We don't allow SALU instructions inside of
; branches.
; FIXME: We are being conservative here. We could allow this in some cases.
; FUNC-LABEL: @add64_in_branch
; SI-CHECK-NOT: S_ADD_I32
; SI-CHECK-NOT: S_ADDC_U32
define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
entry:
%0 = icmp eq i64 %a, 0
br i1 %0, label %if, label %else
if:
%1 = load i64 addrspace(1)* %in
br label %endif
else:
%2 = add i64 %a, %b
br label %endif
endif:
%3 = phi i64 [%1, %if], [%2, %else]
store i64 %3, i64 addrspace(1)* %out
ret void
}