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Fixed a widening bug where we were not using the correct size for the load

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98920 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mon P Wang 2010-03-19 01:19:52 +00:00
parent c28c7689fc
commit c1e5d491a0
2 changed files with 26 additions and 2 deletions
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2
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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@ -2167,7 +2167,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain,
} else
return LdOp;
} else {
unsigned NumElts = WidenWidth / LdWidth;
unsigned NumElts = WidenWidth / NewVTWidth;
EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, VecOp);

26
test/CodeGen/X86/widen_load-2.ll
View File

@ -152,4 +152,28 @@ define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp
%x = add %i8vec31 %a, %b
store %i8vec31 %x, %i8vec31* %ret, align 16
ret void
}
}
%i8vec3pack = type { <3 x i8>, i8 }
define %i8vec3pack @rot() nounwind {
; CHECK: shrb
entry:
%X = alloca %i8vec3pack, align 4
%rot = alloca %i8vec3pack, align 4
%result = alloca %i8vec3pack, align 4
%storetmp = bitcast %i8vec3pack* %X to <3 x i8>*
store <3 x i8> <i8 -98, i8 -98, i8 -98>, <3 x i8>* %storetmp
%storetmp1 = bitcast %i8vec3pack* %rot to <3 x i8>*
store <3 x i8> <i8 1, i8 1, i8 1>, <3 x i8>* %storetmp1
%tmp = load %i8vec3pack* %X
%extractVec = extractvalue %i8vec3pack %tmp, 0
%tmp2 = load %i8vec3pack* %rot
%extractVec3 = extractvalue %i8vec3pack %tmp2, 0
%shr = lshr <3 x i8> %extractVec, %extractVec3
%storetmp4 = bitcast %i8vec3pack* %result to <3 x i8>*
store <3 x i8> %shr, <3 x i8>* %storetmp4
%tmp5 = load %i8vec3pack* %result
ret %i8vec3pack %tmp5
}