From c21e4e197d05c9c9579d9fa5e23482349502c43c Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Thu, 18 Sep 2014 17:34:23 +0000 Subject: [PATCH] Reverting NFC changes from r218050. Instead, the warning was disabled for GCC in r218059, so these changes are no longer required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218062 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64TargetMachine.h | 1 - lib/Target/ARM/ARMTargetMachine.h | 1 - lib/Target/Hexagon/HexagonTargetMachine.h | 1 - lib/Target/MSP430/MSP430TargetMachine.h | 1 - lib/Target/Mips/MipsTargetMachine.h | 1 - lib/Target/NVPTX/NVPTXTargetMachine.h | 1 - lib/Target/PowerPC/PPCTargetMachine.h | 1 - lib/Target/R600/AMDGPUTargetMachine.h | 2 -- lib/Target/Sparc/SparcTargetMachine.h | 1 - lib/Target/SystemZ/SystemZTargetMachine.h | 1 - lib/Target/X86/X86TargetMachine.h | 2 -- lib/Target/XCore/XCoreTargetMachine.h | 1 - 12 files changed, 14 deletions(-) diff --git a/lib/Target/AArch64/AArch64TargetMachine.h b/lib/Target/AArch64/AArch64TargetMachine.h index af692de7430..42d7dc57328 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.h +++ b/lib/Target/AArch64/AArch64TargetMachine.h @@ -31,7 +31,6 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool IsLittleEndian); - using LLVMTargetMachine::getSubtargetImpl; const AArch64Subtarget *getSubtargetImpl() const override { return &Subtarget; } diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h index dfbf45d12fd..3a7887f5edf 100644 --- a/lib/Target/ARM/ARMTargetMachine.h +++ b/lib/Target/ARM/ARMTargetMachine.h @@ -32,7 +32,6 @@ public: CodeGenOpt::Level OL, bool isLittle); - using LLVMTargetMachine::getSubtargetImpl; const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; } /// \brief Register ARM analysis passes with a pass manager. diff --git a/lib/Target/Hexagon/HexagonTargetMachine.h b/lib/Target/Hexagon/HexagonTargetMachine.h index d2bba73c34e..d917d5b89a1 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/lib/Target/Hexagon/HexagonTargetMachine.h @@ -31,7 +31,6 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); - using LLVMTargetMachine::getSubtargetImpl; const HexagonSubtarget *getSubtargetImpl() const override { return &Subtarget; } diff --git a/lib/Target/MSP430/MSP430TargetMachine.h b/lib/Target/MSP430/MSP430TargetMachine.h index 597629d3e81..5c73c831f5e 100644 --- a/lib/Target/MSP430/MSP430TargetMachine.h +++ b/lib/Target/MSP430/MSP430TargetMachine.h @@ -32,7 +32,6 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); - using LLVMTargetMachine::getSubtargetImpl; const MSP430Subtarget *getSubtargetImpl() const override { return &Subtarget; } diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h index 43b62562346..58400cd1b48 100644 --- a/lib/Target/Mips/MipsTargetMachine.h +++ b/lib/Target/Mips/MipsTargetMachine.h @@ -39,7 +39,6 @@ public: void addAnalysisPasses(PassManagerBase &PM) override; - using LLVMTargetMachine::getSubtargetImpl; const MipsSubtarget *getSubtargetImpl() const override { if (Subtarget) return Subtarget; diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.h b/lib/Target/NVPTX/NVPTXTargetMachine.h index 7cc03cb7de8..3dca4da724a 100644 --- a/lib/Target/NVPTX/NVPTXTargetMachine.h +++ b/lib/Target/NVPTX/NVPTXTargetMachine.h @@ -35,7 +35,6 @@ public: const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit); - using LLVMTargetMachine::getSubtargetImpl; const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; } ManagedStringPool *getManagedStrPool() const { diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h index c503ec2fdc7..ea7f27ae18a 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.h +++ b/lib/Target/PowerPC/PPCTargetMachine.h @@ -32,7 +32,6 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); - using LLVMTargetMachine::getSubtargetImpl; const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; } // Pass Pipeline Configuration diff --git a/lib/Target/R600/AMDGPUTargetMachine.h b/lib/Target/R600/AMDGPUTargetMachine.h index 14411e97bb9..ff581b5c9aa 100644 --- a/lib/Target/R600/AMDGPUTargetMachine.h +++ b/lib/Target/R600/AMDGPUTargetMachine.h @@ -33,8 +33,6 @@ public: StringRef CPU, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); ~AMDGPUTargetMachine(); - - using LLVMTargetMachine::getSubtargetImpl; const AMDGPUSubtarget *getSubtargetImpl() const override { return &Subtarget; } diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h index 4b071ba9378..142929ca60e 100644 --- a/lib/Target/Sparc/SparcTargetMachine.h +++ b/lib/Target/Sparc/SparcTargetMachine.h @@ -28,7 +28,6 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit); - using LLVMTargetMachine::getSubtargetImpl; const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; } // Pass Pipeline Configuration diff --git a/lib/Target/SystemZ/SystemZTargetMachine.h b/lib/Target/SystemZ/SystemZTargetMachine.h index 45ff61f6b78..c5f982395a1 100644 --- a/lib/Target/SystemZ/SystemZTargetMachine.h +++ b/lib/Target/SystemZ/SystemZTargetMachine.h @@ -32,7 +32,6 @@ public: CodeGenOpt::Level OL); // Override TargetMachine. - using LLVMTargetMachine::getSubtargetImpl; const SystemZSubtarget *getSubtargetImpl() const override { return &Subtarget; } diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index b7042e1f0a7..8783bab5d95 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -31,8 +31,6 @@ public: StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); - - using LLVMTargetMachine::getSubtargetImpl; const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; } /// \brief Register X86 analysis passes with a pass manager. diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h index e6654f3b062..32360996bba 100644 --- a/lib/Target/XCore/XCoreTargetMachine.h +++ b/lib/Target/XCore/XCoreTargetMachine.h @@ -27,7 +27,6 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); - using LLVMTargetMachine::getSubtargetImpl; const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; } // Pass Pipeline Configuration