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[X86] Fast-ISel was incorrectly always killing the source of a truncate.

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A trunc from i32 to i1 on x86_64 generates an instruction such as

%vreg19<def> = COPY %vreg9:sub_8bit<kill>; GR8:%vreg19 GR32:%vreg9

However, the copy here should only have the kill flag on the 32-bit path, not the 64-bit one.
Otherwise, we are killing the source of the truncate which could be used later in the program.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236890 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Pete Cooper 2015-05-08 18:29:42 +00:00
parent 5c7f7462e4
commit c2347d5cf1
2 changed files with 43 additions and 1 deletions
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4
lib/Target/X86/X86FastISel.cpp
View File

@ -2185,6 +2185,7 @@ bool X86FastISel::X86SelectTrunc(const Instruction *I) {
return true;
}
bool KillInputReg = false;
if (!Subtarget->is64Bit()) {
// If we're on x86-32; we can't extract an i8 from a general register.
// First issue a copy to GR16_ABCD or GR32_ABCD.
@ -2194,11 +2195,12 @@ bool X86FastISel::X86SelectTrunc(const Instruction *I) {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), CopyReg).addReg(InputReg);
InputReg = CopyReg;
KillInputReg = true;
}
// Issue an extract_subreg.
unsigned ResultReg = fastEmitInst_extractsubreg(MVT::i8,
InputReg, /*Kill=*/true,
InputReg, KillInputReg,
X86::sub_8bit);
if (!ResultReg)
return false;

40
test/CodeGen/X86/fast-isel-trunc-kill-subreg.ll Normal file
View File

@ -0,0 +1,40 @@
; RUN: llc %s -o - -fast-isel=true -O1 -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-unknown"
; This test failed the machine verifier because the trunc at the start of the
; method was extracing a subreg and killing the source register. The kill flag was
; invalid here as the source of the trunc could still be used elsewhere.
; CHECK-LABEL: @test
define i32 @test(i32 %block8x8) {
bb:
%tmp9 = trunc i32 %block8x8 to i1
%tmp10 = zext i1 %tmp9 to i32
%tmp11 = mul i32 %tmp10, 8
%tmp12 = zext i32 %tmp11 to i64
br label %bb241
bb241: ; preds = %bb241, %bb
%lsr.iv3 = phi i64 [ %lsr.iv.next4, %bb241 ], [ %tmp12, %bb ]
%lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb241 ], [ 0, %bb ]
%lsr.iv.next2 = add nuw nsw i32 %lsr.iv1, 1
%lsr.iv.next4 = add i64 %lsr.iv3, 32
%exitcond = icmp eq i32 %lsr.iv.next2, 8
br i1 %exitcond, label %.preheader.preheader, label %bb241
.preheader.preheader: ; preds = %bb241
%tmp18 = lshr i32 %block8x8, 1
br label %bb270
bb270: ; preds = %bb270, %.preheader.preheader
%lsr.iv = phi i32 [ %lsr.iv.next, %bb270 ], [ %tmp18, %.preheader.preheader ]
%lsr.iv.next = add i32 %lsr.iv, 4
%tmp272 = icmp slt i32 %lsr.iv.next, 100
br i1 %tmp272, label %bb270, label %.loopexit
.loopexit: ; preds = %bb270
ret i32 0
}