From c2616e43fd980505d3b29b92473d047f878f6708 Mon Sep 17 00:00:00 2001 From: Nate Begeman Date: Mon, 12 May 2008 20:34:32 +0000 Subject: [PATCH] Initial X86 codegen support for VSETCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51000 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 9 ++++++ lib/Target/X86/X86ISelLowering.h | 1 - lib/Target/X86/X86InstrSSE.td | 45 +++++++++++++++++++++++------- 3 files changed, 44 insertions(+), 11 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index f1f12aa1821..5d50e36535a 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -530,6 +530,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand); setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand); setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::VSETCC, (MVT::ValueType)VT, Expand); } if (Subtarget->hasMMX()) { @@ -614,6 +615,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); setOperationAction(ISD::SELECT, MVT::v4f32, Custom); + setOperationAction(ISD::VSETCC, MVT::v4f32, Legal); } if (Subtarget->hasSSE2()) { @@ -639,6 +641,12 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); setOperationAction(ISD::FNEG, MVT::v2f64, Custom); + setOperationAction(ISD::VSETCC, MVT::v2f64, Legal); + setOperationAction(ISD::VSETCC, MVT::v16i8, Legal); + setOperationAction(ISD::VSETCC, MVT::v8i16, Legal); + setOperationAction(ISD::VSETCC, MVT::v4i32, Legal); + setOperationAction(ISD::VSETCC, MVT::v2i64, Legal); + setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); @@ -686,6 +694,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::LOAD, MVT::v2i64, Legal); setOperationAction(ISD::SELECT, MVT::v2f64, Custom); setOperationAction(ISD::SELECT, MVT::v2i64, Custom); + } if (Subtarget->hasSSE41()) { diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 2f08a47ca3b..59cc5163cc2 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -565,7 +565,6 @@ namespace llvm { MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, MachineBasicBlock *BB, unsigned cmovOpc); - }; } diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 0d0c1a528fa..5c1e438f112 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -161,6 +161,22 @@ def PSxLDQ_imm : SDNodeXFormgetValue() >> 3); }]>; +def SSE_CC_imm : SDNodeXFormget()) { + default: Val = 0; assert(0 && "Unexpected CondCode"); break; + case ISD::SETOEQ: Val = 0; break; + case ISD::SETOLT: Val = 1; break; + case ISD::SETOLE: Val = 2; break; + case ISD::SETUO: Val = 3; break; + case ISD::SETONE: Val = 4; break; + case ISD::SETOGE: Val = 5; break; + case ISD::SETOGT: Val = 6; break; + case ISD::SETO: Val = 7; break; + } + return getI8Imm(Val); +}]>; + // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*, // SHUFP* etc. imm. def SHUFFLE_get_shuf_imm : SDNodeXForm; + //===----------------------------------------------------------------------===// // SSE scalar FP Instructions //===----------------------------------------------------------------------===// @@ -855,16 +872,20 @@ let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst" in { def CMPPSrri : PSIi8<0xC2, MRMSrcReg, - (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), - "cmp${cc}ps\t{$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1, - VR128:$src, imm:$cc))]>; + (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), + "cmp${cc}ps\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1, + VR128:$src, imm:$cc))]>; def CMPPSrmi : PSIi8<0xC2, MRMSrcMem, - (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc), - "cmp${cc}ps\t{$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1, - (load addr:$src), imm:$cc))]>; + (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc), + "cmp${cc}ps\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1, + (load addr:$src), imm:$cc))]>; } +def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), VR128:$src2, cond:$cc)), + (CMPPSrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>; +def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), (memop addr:$src2), cond:$cc)), + (CMPPSrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>; // Shuffle and unpack instructions let Constraints = "$src1 = $dst" in { @@ -1675,13 +1696,17 @@ let Constraints = "$src1 = $dst" in { (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), "cmp${cc}pd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1, - VR128:$src, imm:$cc))]>; + VR128:$src, imm:$cc))]>; def CMPPDrmi : PDIi8<0xC2, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc), "cmp${cc}pd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1, - (load addr:$src), imm:$cc))]>; + (load addr:$src), imm:$cc))]>; } +def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), VR128:$src2, cond:$cc)), + (CMPPDrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>; +def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), (memop addr:$src2), cond:$cc)), + (CMPPDrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>; // Shuffle and unpack instructions let Constraints = "$src1 = $dst" in {